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1. 发明授权

US08426268B2 Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
标题翻译：具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成
公开(公告)号：US08426268B2
公开(公告)日：2013-04-23
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

2. 发明申请

US20090189242A1 METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
标题翻译：用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件
公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

3. 发明授权

US07514323B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US07514323B2
公开(公告)日：2009-04-07
申请号：US11164513
申请日：2005-11-28
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

4. 发明授权

US07087532B2 Formation of controlled sublithographic structures 失效
标题翻译：形成受控亚光刻结构
公开(公告)号：US07087532B2
公开(公告)日：2006-08-08
申请号：US10711683
申请日：2004-09-30
申请人： David M Dobuzinsky , Jochen C. Beintner , Siddhartha Panda
发明人： David M Dobuzinsky , Jochen C. Beintner , Siddhartha Panda
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3088 , H01L21/32139 , H01L29/66795 , H01L29/785
摘要： A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.
摘要翻译：用于形成诸如翅片之类的亚光刻结构的工艺使用硬掩模上方的硬掩模保护层来在干蚀刻步骤期间吸收损伤，由此保持硬掩模中的对称性并消除缺陷源。

5. 发明授权

US06656375B1 Selective nitride: oxide anisotropic etch process 失效
标题翻译：选择性氮化物：氧化物各向异性蚀刻工艺
公开(公告)号：US06656375B1
公开(公告)日：2003-12-02
申请号：US09014806
申请日：1998-01-28
申请人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
发明人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
IPC分类号： C23F100
CPC分类号： H01L21/31116
摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.
摘要翻译：用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

6. 发明授权

US6093281A Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers 失效
标题翻译：挡板设计，用于降低等离子体蚀刻室中聚合物前体沉淀过程中的电导损失
公开(公告)号：US6093281A
公开(公告)日：2000-07-25
申请号：US31232
申请日：1998-02-26
申请人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
发明人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
IPC分类号： C23C16/44 , H01J37/32 , C23C16/00
CPC分类号： H01J37/32834 , C23C16/4412 , H01J37/3244
摘要： A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.
摘要翻译：一种用于半导体处理装置的挡板。挡板包括多个狭缝。多个翅片位于相邻狭缝之间。翅片具有不同的高度，并且支撑部分互连翅片。

7. 发明授权

US5747866A Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures 失效
标题翻译：薄晶体Si3N4衬垫在浅沟槽隔离（STI）结构中的应用
公开(公告)号：US5747866A
公开(公告)日：1998-05-05
申请号：US785322
申请日：1997-01-21
申请人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
发明人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/318 , H01L21/32 , H01L21/762 , H01L29/00
CPC分类号： H01L21/3105 , H01L21/32 , H01L21/76224 , Y10S148/05
摘要： Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.
摘要翻译：硅集成电路在浅沟槽隔离（STI）结构中使用氮化硅（Si 3 N 4）的结晶层作为O 2阻挡膜。与沉积的非晶Si3N4相比，晶体Si3N4降低了电子阱的密度。此外，可以沉积更大范围的低压化学气相沉积（LPCVD）Si 3 N 4膜，为厚度可控性提供更大的处理窗口。在720℃至780℃的温度下沉积LPCVD-Si 3 N 4膜。沉积膜处于非晶状态。随后，在1050℃至1100℃下进行纯氮或氨的高温快速热退火60秒。

8. 发明授权

US5536360A Method for etching boron nitride 失效
标题翻译：氮化硼蚀刻方法
公开(公告)号：US5536360A
公开(公告)日：1996-07-16
申请号：US368254
申请日：1995-01-03
申请人： Son V. Nguyen , David M. Dobuzinsky
发明人： Son V. Nguyen , David M. Dobuzinsky
IPC分类号： C04B41/91 , C30B29/38 , C30B33/00 , H01L21/306 , H01L21/308 , H01L21/311 , H01L21/3115
CPC分类号： H01L21/31116 , Y10S148/113
摘要： The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.
摘要翻译：本发明提供了一种增强氮化硼蚀刻速率的方法，该方法包括用元素周期表IVA族元素（例如硅，碳或锗）掺杂一氮化硼层。掺杂的氮化硼层可以以比在掺杂氮化硼之前可能的热磷酸更快地被湿法蚀刻。

9. 发明授权

US07592245B2 Poly filled substrate contact on SOI structure 失效
标题翻译：多晶硅填充衬底接触SOI结构
公开(公告)号：US07592245B2
公开(公告)日：2009-09-22
申请号：US12014127
申请日：2008-01-15
申请人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
发明人： David M. Dobuzinsky , Byeong Y. Kim , Effendi Leobandung , Munir D. Naeem , Brian L. Tessier
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译：本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。绝缘子表面水平高于最终结构。接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。具体地，多晶硅的厚度大于基板接触孔的尺寸。接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。所述多晶硅的蚀刻不与衬底接触。绝缘体的过剩被抛光到所需的水平。

10. 发明授权

US07560360B2 Methods for enhancing trench capacitance and trench capacitor 失效
标题翻译：增加沟槽电容和沟槽电容的方法
公开(公告)号：US07560360B2
公开(公告)日：2009-07-14
申请号：US11468472
申请日：2006-08-30
申请人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
发明人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L28/84 , H01L29/66181
摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.
摘要翻译：公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。在一个实施例中，一种方法包括形成沟槽的第一部分; 在第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

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