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1. 发明授权

US5737636A Method and system for detecting bypass errors in a load/store unit of a superscalar processor 失效
标题翻译：用于检测超标量处理器的加载/存储单元中的旁路错误的方法和系统
公开(公告)号：US5737636A
公开(公告)日：1998-04-07
申请号：US591249
申请日：1996-01-18
申请人： David George Caffo , Christopher Anthony Freymuth
发明人： David George Caffo , Christopher Anthony Freymuth
IPC分类号： G06F9/38 , G06F12/08 , G06F13/16
CPC分类号： G06F9/3834 , G06F12/0802
摘要： A load queue is provided in a load/store unit of a superscalar processor that includes a real page number buffer for storing a real page number for each instruction entry in the load queue. The load queue also includes a real page number comparator coupled to the real page number buffer for comparing executing load instruction entries with queued load instruction entries in the load queue. The load queue further includes a cache line modified register coupled to the data cache. The cache line modified register marks the queued load instruction entries when a cache line of the data cache addressed by the queued load instruction entry has been modified. In a preferred embodiment, when the executing load instruction is out of program order with respect to one of the queued load instructions, and the modified cache line register has marked the queued load instruction, the load queue signals a sequencer unit to cancel the queued load instruction. The load queue further includes an instruction identification buffer coupled to a sequencer unit for storing an instruction identifier for each entry in the load queue and a program order comparator coupled to the instruction identification buffer. The program comparator compares the ordering of instruction entries in the load queue with the executing load or store instruction.
摘要翻译：在超标量处理器的加载/存储单元中提供加载队列，其包括用于存储加载队列中的每个指令条目的实际页号的实际页号缓冲器。加载队列还包括耦合到实际页号码缓冲器的实际页码比较器，用于将执行的加载指令条目与加载队列中的排队加载指令条目进行比较。加载队列还包括耦合到数据高速缓存的高速缓存线修改寄存器。高速缓存行修改的寄存器在排队的加载指令条目寻址的数据缓存的高速缓存行已被修改时标记排队的加载指令条目。在优选实施例中，当执行加载指令相对于排队的加载指令之一超出程序次序时，并且修改的高速缓存行寄存器已经标记了排队的加载指令，则加载队列发送定序器单元来取消排队的加载指令。加载队列还包括指令识别缓冲器，其耦合到定序器单元，用于存储加载队列中的每个条目的指令标识符以及耦合到指令识别缓冲器的程序顺序比较器。程序比较器将负载队列中的指令条目的顺序与执行的加载或存储指令进行比较。

2. 发明授权

US5751946A Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor 失效
标题翻译：用于检测超标量处理器的加载/存储单元中的旁路错误状况的方法和系统
公开(公告)号：US5751946A
公开(公告)日：1998-05-12
申请号：US588183
申请日：1996-01-18
申请人： Muhammad Afsar , Christopher Anthony Freymuth
发明人： Muhammad Afsar , Christopher Anthony Freymuth
IPC分类号： G06F9/38 , G06F11/28
CPC分类号： G06F9/3834
摘要： A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match. The completion logic receives the executing store instruction and a bypass error signal when the load instruction has executed out-of-order with respect to the executing store instruction. The completion logic also receives the identifier of the load instruction which bypassed the executing store instruction.
摘要翻译：一种用于检测超标量处理器的加载/存储单元中的旁路错误状况的方法，包括：当实际地址到加载指令的字边界时，确定加载指令是否相对于执行存储指令执行无序，执行存储指令的字边界的真实地址匹配，以及当所述加载指令相对于执行存储指令执行无序时，识别所述加载指令的旁路错误条件。在系统方面，系统包括负载队列，检测逻辑和完成逻辑。负载队列包括用于将实际地址存储到每个执行的加载指令的字边界的实际页号缓冲器。检测逻辑将实际地址与针对执行存储指令的加载指令的字边界进行比较，并且当实际地址到字边界匹配时，将加载指令的程序顺序和执行存储指令进行比较。当加载指令相对于执行存储指令执行无序时，完成逻辑接收执行存储指令和旁路错误信号。完成逻辑还接收绕过执行存储指令的加载指令的标识符。

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