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1. 发明授权

US06486007B2 Method of fabricating a memory cell for a static random access memory 有权
标题翻译：制造用于静态随机存取存储器的存储单元的方法
公开(公告)号：US06486007B2
公开(公告)日：2002-11-26
申请号：US09910396
申请日：2001-07-20
申请人： Tsiu Chiu Chan , Mehdi Zamanian , David Charles McClure
发明人： Tsiu Chiu Chan , Mehdi Zamanian , David Charles McClure
IPC分类号： H01L21335
CPC分类号： H01L27/11 , G11C11/412
摘要： A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
摘要翻译：公开了一种用于静态随机存取存储器的存储单元的方法。存储单元包括连接在一起以形成锁存器的一对交叉耦合CMOS逻辑反相器，以及连接到逻辑反相器的一对p沟道传输栅极晶体管，用于选择性地提供对锁存器的访问。存储单元的布局包括存储单元的p沟道晶体管位于其中的矩形有源区。矩形有源区域沿着一行存储器单元邻接相邻存储器单元的类似有效区域，以形成用于p沟道存储单元晶体管的单个矩形有源区域。矩形有源区减少了不利地影响存储单元的性能的制造相关现象的发生。

2. 发明授权

US6101618A Method and device for acquiring redundancy information from a packaged memory chip 失效
标题翻译：用于从封装的存储器芯片获取冗余信息的方法和装置
公开(公告)号：US6101618A
公开(公告)日：2000-08-08
申请号：US172848
申请日：1993-12-22
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C29/00 , G11C29/02 , G11C29/44 , H02H3/05
CPC分类号： G11C29/835 , G11C29/02 , G11C29/44 , G11C2029/0403
摘要： A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.
摘要翻译：用于测试封装的半导体存储器件的方法和电路允许通过在封装的存储器芯片上执行三个可能的冗余卷积测试之一来获取关于冗余元件的信息。通过刺激封装器件的引脚，存储器芯片被设置为三种测试模式之一。在第一测试模式中，感测到指示冗余的预置信号，并且输出引脚的状态改变。在第二测试模式中，当冗余行被寻址时，存储器阵列行被顺序寻址并且输出引脚的状态被改变。在第三个测试中，顺序寻址阵列列，并且当冗余列被寻址时，更改冗余列映射到的输出引脚的状态。

3. 发明授权

US5905683A Method and structure for recovering smaller density memories from larger density memories 失效
标题翻译：从较大密度存储器中回收较小密度存储器的方法和结构
公开(公告)号：US5905683A
公开(公告)日：1999-05-18
申请号：US940045
申请日：1997-09-29
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C11/413 , G11C8/12 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/789 , G11C29/88 , G11C8/12 , G11C29/76
摘要： Therefore, according to the present invention, one or more bond pads of a memory device are connected to a corresponding address buffer or address buffers by a selection circuit which selectively allows the address buffer to ignore a signal on the bond pad. In order to define a smaller density memory device, the signal on the bond pad is ignored, and the selection circuit internally forces a logic state on the address buffer which points to the desired smaller density memory device. The memory devices and the smaller density memory devices are packaged and bonded identically and then sorted and branded such that it is not necessary to use the double inking technique. The present invention may be applied to a plurality of bond pads and corresponding address buffers. According to a preferred embodiment of the invention, the selection circuit has of a plurality of fuses which may be selectively blown to cause the address buffer to ignore a signal on the bond pad. Nonvolatile devices such as EPROM, EEPROM, Flash EPROM, or PROM devices may also be used instead of fuses. The present invention can make use of ESD transistors, or nonvolatile devices, and fuses.
摘要翻译：因此，根据本发明，存储器件的一个或多个接合焊盘通过选择电路连接到相应的地址缓冲器或地址缓冲器，该选择电路选择性地允许地址缓冲器忽略接合焊盘上的信号。为了定义较小的密度存储器件，接合焊盘上的信号被忽略，并且选择电路在内部强制地址缓冲器上的逻辑状态，其指向所需的较小密度存储器件。存储器件和较小密度存储器件被相同地封装和粘合，然后进行分类和标记，使得不需要使用双重上墨技术。本发明可以应用于多个接合焊盘和相应的地址缓冲器。根据本发明的优选实施例，选择电路具有多个熔丝，其可被选择性地熔断以使地址缓冲器忽略接合焊盘上的信号。还可以使用诸如EPROM，EEPROM，闪存EPROM或PROM设备的非易失性设备来代替保险丝。本发明可以使用ESD晶体管，非易失性器件和保险丝。

4. 发明授权

US5835427A Stress test mode 失效
标题翻译：压力测试模式
公开(公告)号：US5835427A
公开(公告)日：1998-11-10
申请号：US172854
申请日：1993-12-22
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memory cells. All active devices in the memory device are turned off or limited to linear region operation. This allows a supervoltage to be applied to the wordlines with internal nodes of the memory cells held low by the bitlines, stressing an oxide barrier between memory cells and wordlines without damaging active devices due to the supervoltage.
摘要翻译：集成电路存储器件中处理缺陷的加速故障是通过断言存储器件的所有字线来实现多个存储器单元的所有通过门。然后将所有位线拉低以拉低多个存储器单元中的所有内部节点。存储器件中的所有有源器件都被关闭或被限制在线性区域操作。这允许将超电压施加到字线，其中由位线保持低电平的存储器单元的内部节点，强调存储器单元和字线之间的氧化物屏障，而不会由于超压而损坏有源器件。

5. 发明授权

US5712584A Synchronous stress test control 失效
标题翻译：同步应力测试控制
公开(公告)号：US5712584A
公开(公告)日：1998-01-27
申请号：US589015
申请日：1996-01-19
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/14 , H03K3/037 , H03K19/00 , H03K19/096 , H03K5/13
CPC分类号： G01R31/318555
摘要： The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode. The logic state of the clock signal is controlled by a clock control circuit which sets the logic state of the clock as a function of whether the device is in a test mode. Thus, the master clock signal which controls the master latch element and the clock signal which controls the slave latch element are controlled such that the master latch and the slave latch conduct simultaneously for proper and full initialization of the device data path upon power-up of the device in a test mode.
摘要翻译：本发明确保了在测试模式下上电时初始化由主锁存器和从锁存器组成的同步集成电路装置的整个数据路径，从而克服了现有技术的装置数据路径不初始化的问题。在测试模式下，主时钟信号在内部初始化为同步集成电路器件，以允许主器件锁存器导通。作为主时钟信号的导数的时钟信号被控制为等于第一逻辑状态，以便控制同步集成电路器件的从锁存元件进行导通，而与主时钟信号的状态无关。将时钟信号控制为等于第一逻辑状态允许时钟信号能够控制从锁存元件，使得集成电路器件的整个数据路径在测试模式下在器件上电时被初始化。时钟信号的逻辑状态由时钟控制电路控制，时钟控制电路根据设备是否处于测试模式来设置时钟的逻辑状态。因此，控制主锁存元件的主时钟信号和控制从锁存元件的时钟信号被控制，使得主锁存器和从锁存器同时进行，用于在加电时对器件数据路径的适当和完全初始化该设备处于测试模式。

6. 发明授权

US07411433B2 Reset ramp control 有权
标题翻译：复位斜坡控制
公开(公告)号：US07411433B2
公开(公告)日：2008-08-12
申请号：US11012693
申请日：2004-12-15
申请人： David Charles McClure , Rong Yin
发明人： David Charles McClure , Rong Yin
IPC分类号： H03K17/22
CPC分类号： H03K5/2481 , H03K17/223
摘要： A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.
摘要翻译：描述了复位斜坡控制结构和方法。检测到监控电压的快速下降条件，并用于强制系统复位状态。快速斜坡检测与系统复位强制之间的延迟可调。操作适应于包括所有直流电源系统。当标准复位电路可能不可操作时，复位斜坡控制结构在快速下降条件下提供操作保护。

7. 发明授权

US06252447B1 Edge transition detection circuit with variable impedance delay elements 失效
标题翻译：具有可变阻抗延迟元件的边沿转换检测电路
公开(公告)号：US06252447B1
公开(公告)日：2001-06-26
申请号：US09139225
申请日：1998-08-25
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03K708
CPC分类号： H03K5/133
摘要： According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.
摘要翻译：根据本发明，通过将一个或多个延迟信号的逻辑状态设置为适当的值，可以修改整个具有分布式电路块的集成电路中的多个电源延迟元件的电阻值，以产生所需的延迟时间或脉冲整个集成电路的宽度调整。将延迟信号设置到所需逻辑状态可以通过各种手段来实现，包括强制测试焊盘达到逻辑电平，熔断熔丝或进入测试模式。

8. 发明授权

US5995444A Edge transition detection control of a memory device 失效
标题翻译：存储器件的边沿转换检测控制
公开(公告)号：US5995444A
公开(公告)日：1999-11-30
申请号：US547
申请日：1997-12-30
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.
摘要翻译：通过改变存储器件的一个或多个控制信号的逻辑状态可选择地改变存储器件的内部边沿转变检测信号的脉冲宽度。由存储器件的输入缓冲器产生的多个边沿转变检测信号通过例如通过有线NOR或有线NAND配置被配线配置在一起，以产生一个或多个边缘转换检测总线。将一个或多个边缘跃迁检测总线以及两个或更多个控制信号引入到边缘切换检测驱动器，其确定生成供整个存储器件使用的器件边沿转变检测信号的逻辑状态。改变控制信号的逻辑状态的组合允许设备边沿转变检测信号的脉冲宽度可选择地变化。

9. 发明授权

US5841789A Apparatus for testing signal timing and programming delay 失效
标题翻译：用于测试信号定时和编程延迟的装置
公开(公告)号：US5841789A
公开(公告)日：1998-11-24
申请号：US647222
申请日：1996-05-09
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G01R31/30 , G06F11/00 , G11C29/02 , G11C29/44 , G11C29/50 , G01R31/28 , G11C29/00
CPC分类号： G11C29/026 , G01R31/30 , G06F11/006 , G11C29/02 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50012 , G11C11/401 , G11C11/41
摘要： A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.
摘要翻译：公开了用于测试和编程信号定时的方法和装置，其可以使用片上定时指令信号和脉冲并入集成电路装置。本发明的方法能够在生产测试期间以各种运行速度进行设备的非永久性测试和重新测试。在重新测试期间，由于不可修复的错误，临时信号延迟被选择性地引入到先前测试失败的设备的电路中。一旦设备无错误地通过生产测试或具有可修复的错误，临时信号延迟将被永久地编程到设备中。具体地，该方法利用一个或多个模式控制电路和测试电压输入端子来非永久地选择可以在稍后时间被识别并永久启用的信号延迟。

10. 发明授权

US5666482A Method and system for bypassing a faulty line of data or its associated tag of a set associative cache memory 失效
标题翻译：用于绕过故障线路数据的方法和系统或其关联的高速缓冲存储器的关联标签
公开(公告)号：US5666482A
公开(公告)日：1997-09-09
申请号：US719734
申请日：1996-09-25
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G06F12/08 , G06F12/12 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/88 , G06F12/126 , G06F2212/1032
摘要： According to the present invention, faulty lines of data of a set associative cache memory containing one or more faulty data bits which are not repairable through conventional repair means such as row/column redundancy, are not updated following a cache miss condition and thereby effectively bypassed. Replacement logic circuitry detects and controls the state of a replacement status bit associated with each line of data of the set associative cache memory to determine if the line of data in the cache should be updated or bypassed. Thus, when replacing a line of data, the replacement logic circuitry detects the address of a faulty line of data in a particular set and avoids updating that faulty line of data in favor of updating another line of data of another set. The replacement logic circuitry may be used with a variety of replacement algorithms including the least recently used (LRU) replacement algorithm, the first in first out (FIFO) replacement algorithm, the last in first out (LIFO) replacement algorithm, the random replacement algorithm, or the pseudo LRU replacement algorithm.
摘要翻译：根据本发明，通过诸如行/列冗余的常规修复装置不可修复的包含一个或多个故障数据位的组合的联想高速缓冲存储器的数据线的故障线在高速缓存未命中状态之后不被更新，从而有效地绕过。替换逻辑电路检测和控制与所设置的联想高速缓冲存储器的每条数据相关联的替换状态位的状态，以确定高速缓存中的数据行是否应被更新或绕过。因此，当替换一行数据时，替换逻辑电路检测特定集合中有故障的数据行的地址，并且避免更新该错误的数据行，以有利于更新另一组的另一数据行。替换逻辑电路可以与各种替换算法一起使用，包括最近最少使用的（LRU）替换算法，先进先出（FIFO）替换算法，最先进先出（LIFO）替换算法，随机替换算法，或伪LRU替换算法。

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