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1. 发明授权

US08196417B2 Refrigerator 有权
标题翻译：冰箱
公开(公告)号：US08196417B2
公开(公告)日：2012-06-12
申请号：US12094760
申请日：2006-11-23
申请人： Dong-Kyu Kim , Kyung-Dae Hwang , Jin-Hyun Kim , Hyuk-Soon Kim , Seung-Beom Chae , Hyun-Tae Lee , Joo-Shin Kim
发明人： Dong-Kyu Kim , Kyung-Dae Hwang , Jin-Hyun Kim , Hyuk-Soon Kim , Seung-Beom Chae , Hyun-Tae Lee , Joo-Shin Kim
IPC分类号： F24F3/16
CPC分类号： F25D17/042
摘要： The present invention relates to a refrigerator, including: a refrigerating cycle having an evaporator (1a); a space for exchanging heat with the evaporator; a region for exchanging heat between the evaporator and the space; and a storage chamber and a door for defining the space, wherein at least one of the region, the storage chamber and the door has undergone at least one of a Kimchi lactic acid bacteria culture treatment and a Kimchi lactic acid bacteria culture exposure treatment.
摘要翻译：本发明涉及一种冰箱，包括：具有蒸发器（1a）的制冷循环; 与蒸发器交换热量的空间; 用于在蒸发器和空间之间交换热量的区域; 以及用于限定空间的储存室和门，其中，所述区域，储存室和所述门中的至少一个已经经过泡菜乳酸菌培养处理和泡菜乳酸菌培养暴露处理中的至少一种。

2. 发明申请

US20110151318A1 Secondary battery 有权
标题翻译：二次电池
公开(公告)号：US20110151318A1
公开(公告)日：2011-06-23
申请号：US12801796
申请日：2010-06-25
申请人： Chi-Young Lee , Sang-Eun Cheon , Seok-Yoon Yoo , Yoon-Tai Kwak , Dong-Wook Kim , Jong-Seok Moon , Sang-Dae Hwang , Tatsuya Hashimoto
发明人： Chi-Young Lee , Sang-Eun Cheon , Seok-Yoon Yoo , Yoon-Tai Kwak , Dong-Wook Kim , Jong-Seok Moon , Sang-Dae Hwang , Tatsuya Hashimoto
IPC分类号： H01M2/02 , H01M4/02
CPC分类号： H01M2/263 , H01M2/266 , H01M10/0431 , H01M10/052
摘要： A secondary battery including an electrode assembly, the electrode assembly including electrode plates and a separator interposed between the electrode plates, at least one of the electrode plates including a coated part, the coated part including a metallic plate having an active material coated thereon, and an uncoated part, the uncoated part including a metallic plate without active material coated thereon, the uncoated part including a folding line in the uncoated part, and a folding part with an end portion folded with respect to the folding line; and a current collector electrically contacting the folding part.
摘要翻译：一种二次电池，其包括电极组件，所述电极组件包括电极板和插入在所述电极板之间的隔膜，所述电极板中的至少一个包括涂覆部分，所述涂覆部分包括其上涂覆有活性材料的金属板，以及未涂覆部分，所述未涂覆部分包括没有涂覆有活性材料的金属板，所述未涂覆部分包括所述未涂覆部分中的折叠线，以及折叠部分，所述折叠部分具有相对于所述折叠线折叠的端部; 以及集电器电接触折叠部分。

3. 发明申请

US20080101109A1 Phase Change Memory, Phase Change Memory Assembly, Phase Change Memory Cell, 2D Phase Change Memory Cell Array, 3D Phase Change Memory Cell Array and Electronic Component 有权
标题翻译：相变存储器，相变存储器组件，相变存储器单元，2D相变存储器单元阵列，3D相变存储器单元阵列和电子部件
公开(公告)号：US20080101109A1
公开(公告)日：2008-05-01
申请号：US10576760
申请日：2004-10-19
申请人： Peter Haring-Bolivar , Bernard Bechevet , Veronique Sousa , Dae-Hwang Kim , Heinrich Kurz , Florian Merget
发明人： Peter Haring-Bolivar , Bernard Bechevet , Veronique Sousa , Dae-Hwang Kim , Heinrich Kurz , Florian Merget
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1226 , H01L45/1246 , H01L45/144 , H01L45/1675
摘要： A phase change memory having a memory material layer consisting of a phase change material, and a first and second electrical contact which are located at a distance from one another and via which a switching zone of the memory material layer can be traversed by a current signal, wherein the current signal can be used to induce a reversible phase change between a crystalline phase and an amorphous phase and thus a change in resistance of the phase change material in the switching zone. The invention also relates to a phase change memory assembly, a phase change memory cell, a 2D phase change memory cell array, a 3D phase change memory cell array and an electronic component.
摘要翻译：一种相变存储器，具有由相变材料构成的存储材料层，以及位于彼此间隔一定距离的第一和第二电接点，存储材料层的开关区域可以通过电流信号其中电流信号可用于在晶相和非晶相之间引起可逆相变，从而在开关区中引起相变材料的电阻变化。本发明还涉及相变存储器组件，相变存储单元，2D相变存储单元阵列，3D相变存储单元阵列和电子组件。

4. 发明申请

US20050141548A1 Media access control apparatus and method for guaranteeing quality of service in wireless LAN 有权
标题翻译：用于保证无线LAN服务质量的媒体访问控制装置和方法
公开(公告)号：US20050141548A1
公开(公告)日：2005-06-30
申请号：US10917684
申请日：2004-08-12
申请人： Ki Koo , Dae Hwang
发明人： Ki Koo , Dae Hwang
IPC分类号： H04L12/28 , H04L12/413 , H04L12/56 , H04L12/66
CPC分类号： H04W72/1242 , H04W28/14 , H04W84/12
摘要： The present invention relates to a media access control (MAC) apparatus and method for guaranteeing quality-of-service in a wireless local area network (LAN). The MAC method comprises: extracting a user priority from a frame received from an upper layer and separately storing a voice frame and a general frame according to an access category (AC); independently performing backoff operations for the voice frame and the general frame; determining whether the backoff operations for the voice frame and the general frame have simultaneously ended; if the backoff operations have simultaneously ended, transmitting the voice frame having a higher priority first and performing the backoff operation for the general frame; and if the backoff operations have not simultaneously ended, transmitting a frame whose backoff operation ends.
摘要翻译：本发明涉及一种用于保证无线局域网（LAN）中的服务质量的媒体接入控制（MAC）装置和方法。 MAC方法包括：根据接入类别（AC）从上层接收的帧中提取用户优先级，并单独存储语音帧和一般帧; 独立执行语音帧和通用帧的退避操作; 确定语音帧和一般帧的退避操作是否同时结束; 如果退避操作已经同时结束，则首先发送具有较高优先级的语音帧，并对一般帧执行退避操作; 并且如果退避操作没有同时结束，则发送退避操作结束的帧。

5. 发明授权

US06803893B1 Scan rate controller 失效
标题翻译：扫描速率控制器
公开(公告)号：US06803893B1
公开(公告)日：2004-10-12
申请号：US08992955
申请日：1997-12-18
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G336
CPC分类号： G09G3/3611 , G09G3/3674 , G09G5/008 , G09G5/022 , G09G5/399 , G09G2340/0407 , G09G2340/0435 , G09G2360/02
摘要： A scan rate controller includes a write phase lock loop for generating a write clock signal, a read timing generator for generating a fixed read timing clock signal, and a frame memory for storing a video signal according to the write clock signal from the write phase lock loop and a write timing clock signal from a timing generator, and outputting the video signal according to the read timing clock signal from read timing generator, thereby converting an image size in accordance with various video modes into an image size corresponding to a fixed video mode.
摘要翻译：扫描速率控制器包括用于产生写入时钟信号的写入锁相环，用于产生固定的读取定时时钟信号的读取定时发生器和用于根据来自写入锁相位的写时钟信号存储视频信号的帧存储器循环和来自定时发生器的写定时时钟信号，并且根据来自读定时发生器的读定时时钟信号输出视频信号，从而将根据各种视频模式的图像大小转换为与固定视频模式相对应的图像大小。

6. 发明授权

US06251642B1 Continuous process for preparing optically pure (S)-3-hydroxy-&ggr;-butyrolactone 失效
标题翻译：制备光学纯（S）-3-羟基-γ-丁内酯的连续方法
公开(公告)号：US06251642B1
公开(公告)日：2001-06-26
申请号：US09359712
申请日：1999-07-23
申请人： Jongpil Chun , Yik-haeng Cho , Kyoung Rok Roh , Young Mi Park , Hosung Yu , Dae Hwang, II
发明人： Jongpil Chun , Yik-haeng Cho , Kyoung Rok Roh , Young Mi Park , Hosung Yu , Dae Hwang, II
IPC分类号： C12P1704
CPC分类号： C07D307/33 , C07B2200/07 , C12P7/42 , C12P17/04 , C12P19/14 , C12P19/22
摘要： The present invention relates to a continuous process for preparing optically pure (S)-3-hydroxy-&ggr;-butyrolactone expressed by the following Formula 1 and more particularly, to a process which enables preparing optically pure (S)-3-hydroxy-&ggr;-butyrolactone economically in large quantities, by: (a) Preparing &agr;-(1,4) linked oligosaccharide with adequate sugar distribution by reacting amylopectin which is easily available from natural product with enzyme under a specific condition; and (b) Performing oxidation, esterification and cyclization sequentially under a specific condition.
摘要翻译：本发明涉及用于制备由下式1表示的光学纯的（S）-3-羟基-γ-丁内酯的连续方法，更具体地说，涉及能够制备光学纯的（S）-3-羟基-γ-丁内酯通过以下方式经济地制备γ-丁内酯：（a）通过在天然产物中容易获得的支链淀粉与酶在特定条件下反应制备具有足够糖分布的α-（1,4）连接的寡糖; 和（b）在特定条件下依次进行氧化，酯化和环化。

7. 发明授权

US06201535B1 Flat panel display apparatus with automatic tracking control 有权
标题翻译：具有自动跟踪控制的平板显示设备
公开(公告)号：US06201535B1
公开(公告)日：2001-03-13
申请号：US09246133
申请日：1999-02-08
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G500
CPC分类号： G09G5/008
摘要： A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a delay circuit for delaying the sampling clock signal, a level converter for converting an analog video signal supplied from the host to have a given digital voltage level, a phase detector for detecting the phase difference between the digital voltage level video signal from the level converter and the sampling clock signal delayed by the delay circuit to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal, a micro-controller for generating the delay data to increase or decrease the delay time of the delay circuit to adjust the phase of the sampling clock signal in response to the output of the comparator, and an analog to digital converter for converting the analog video signal into corresponding digital video signal in response to the delayed sampling clock signal.
摘要翻译：平板显示装置包括：采样时钟发生器，用于产生具有对应于从主机提供的同步信号的频率的采样时钟信号，用于延迟采样时钟信号的延迟电路;电平转换器，用于转换从主机具有给定的数字电压电平，相位检测器，用于检测来自电平转换器的数字电压电平视频信号与由延迟电路延迟的采样时钟信号之间的相位差，以产生相位差数据;比较器，用于比较所述相位差数据具有对应于所述同步信号的延迟数据;微控制器，用于产生所述延迟数据以增加或减少所述延迟电路的延迟时间，以响应于所述延迟电路的输出来调整所述采样时钟信号的相位比较器和用于将模拟视频信号转换成相应的数字视频的模数转换器响应于延迟的采样时钟信号而被点亮。

8. 发明授权

US6160542A Tracking control circuit of a display 有权
标题翻译：跟踪显示器的控制电路
公开(公告)号：US6160542A
公开(公告)日：2000-12-12
申请号：US204345
申请日：1998-12-04
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G3/36 , G09G3/20 , G09G5/00
CPC分类号： G09G5/008
摘要： A display includes: a clock signal generator for generating a first sampling clock signal used for converting an analog video signal supplied from a host to a digital video signal; a tracking control circuit for generating tracking control data corresponding to a tracking adjustment key input; an A/D converter for converting the analog video signal to the digital video signal in synchronism with a second clock signal obtained by delaying the first sampling clock signal according to the tracking control data; a high frequency clock signal generator for generating a high frequency clock signal, and the tracking control circuit measuring the presently delayed time of the second sampling clock signal by means of the high frequency clock signal so as to adjust the delayed time according to the tracking control data.
摘要翻译：显示器包括：时钟信号发生器，用于产生用于将从主机提供的模拟视频信号转换为数字视频信号的第一采样时钟信号; 跟踪控制电路，用于产生对应于跟踪调整键输入的跟踪控制数据; A / D转换器，用于与根据跟踪控制数据延迟第一采样时钟信号而获得的第二时钟信号同步地将模拟视频信号转换成数字视频信号; 用于产生高频时钟信号的高频时钟信号发生器，并且跟踪控制电路借助于高频时钟信号测量第二采样时钟信号的当前延迟时间，以便根据跟踪控制调整延迟时间数据。

9. 发明授权

US5966119A Pseudo-synchronizing signal generator for use in digital image processing apparatus 失效
标题翻译：用于数字图像处理装置的伪同步信号发生器
公开(公告)号：US5966119A
公开(公告)日：1999-10-12
申请号：US759598
申请日：1996-12-05
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： H04N5/06 , G09G5/00 , G09G5/18 , H04N3/227 , H04N5/12 , H04N5/04
CPC分类号： H04N5/123
摘要： A pseudo-synchronizing signal generator for use in a digital image processing apparatus is disclosed. The pseudo-synchronizing signal generation circuit comprising a pulse generating circuit for generating a train of predetermined pulses as being a dot clock oscillation signal for use with a digital image processing apparatus in response to a synchronizing signal input from an external source, a counting controller disposed to input a program data signal for synchronizing the program data signal with a pulse output by the pulse generating circuit and for outputting a program data enable signal, a down counter enabled by the program data enable signal synchronized with the clot clock oscillation signal so as to count down from a preset value, a detector for detecting when the down counting operation of the down counter reaches zero for generating a disable signal to be applied to the down counter and for generating a first pseudo-synchronizing signal, and a multiplexer to selectively outputting, as a second pseudo-synchronizing signal, a selected one of the first pseudo-synchronizing signal and the horizontal synchronizing signal in responsive to the program data signal. As a result, the circuit is able to generate a pseudo-synchronizing signal having a predetermined delay time duration with respect to its inherent synchronizing signal, in synchronization with a train of dot clock oscillation signal, thereby enabling a digital image processing apparatus to perform a positioning of a pictorial image being display on a variable visual monitor.
摘要翻译：公开了一种用于数字图像处理装置的伪同步信号发生器。伪同步信号产生电路包括：脉冲发生电路，用于响应于从外部源输入的同步信号，产生预定脉冲序列作为与数字图像处理装置一起使用的点时钟振荡信号;计数控制器输入用于使程序数据信号与由脉冲发生电路输出的脉冲同步的程序数据信号，并输出程序数据使能信号，通过与凝块时钟振荡信号同步的程序数据使能信号使能的递减计数器，以便从预设值向下计数的检测器，用于检测下降计数器的向下计数操作何时达到零以产生要施加到递减计数器的禁用信号并用于产生第一伪同步信号的检测器，以及多路复用器选择性地输出作为第二伪同步信号，选择第一伪同步信号si 并且响应于程序数据信号的水平同步信号。结果，电路能够与点阵时钟振荡信号同步地产生具有相对于其固有同步信号的预定延迟持续时间的伪同步信号，从而使数字图像处理装置执行在可变的视觉监视器上显示图形图像的定位。

10. 发明授权

US5790112A Oscillation and trigger circuit for vertical synchronizing signal 失效
标题翻译：用于垂直同步信号的振荡和触发电路
公开(公告)号：US5790112A
公开(公告)日：1998-08-04
申请号：US648504
申请日：1996-05-15
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： H03K3/282 , H03K5/13 , H04N5/04 , G09G5/00
CPC分类号： H03K5/13 , H04N5/04
摘要： An oscillation and trigger circuit for a vertical synchronizing signal in a display apparatus, the oscillation and trigger circuit comprising: a pulse generator for generating a single pulse for each active cycle of the vertical synchronizing signal; a first signal detector having an input terminal connected to an output terminal of the pulse generator, for determining a state of no input of the vertical synchronizing signal whose frequency is less than a predetermined frequency and for generating a first predetermined signal indicative of the state; a second signal detector having input terminals connected to respective output terminals of the pulse generator and the first signal detector, for checking a time interval of the vertical synchronizing signal input to the pulse generator so as to output a second predetermined signal when the time interval exceeds a predetermined time period and for outputting the second predetermined signal responsive to the first predetermined signal input from the first signal detector; an input signal detector connected to the first signal detector, for determining an input of the vertical synchronizing signal; a multiplexer having a selection input terminal connected to receive the second predetermined signal output from an output terminal of the second signal detector, for selecting for output one of a first clock signal of a predetermined frequency and the vertical synchronizing signal; and a vertical oscillator having an input terminal connected to an output terminal of the multiplexer, for generating a vertical oscillation signal of a predetermined frequency in response to the selected one of the clock signal and the vertical synchronizing signal selected by the multiplexer.
摘要翻译：一种用于显示装置中的垂直同步信号的振荡和触发电路，所述振荡和触发电路包括：脉冲发生器，用于为所述垂直同步信号的每个有效周期产生单个脉冲; 第一信号检测器，其具有连接到脉冲发生器的输出端的输入端，用于确定频率小于预定频率的垂直同步信号的无输入状态，并产生指示状态的第一预定信号; 第二信号检测器，其具有连接到脉冲发生器和第一信号检测器的相应输出端的输入端，用于检查输入到脉冲发生器的垂直同步信号的时间间隔，以便当时间间隔超过时输出第二预定信号预定时间段，并响应于从第一信号检测器输入的第一预定信号输出第二预定信号; 连接到第一信号检测器的输入信号检测器，用于确定垂直同步信号的输入; 多路复用器，其具有选择输入端，连接用于接收从第二信号检测器的输出端输出的第二预定信号，用于选择输出预定频率的第一时钟信号和垂直同步信号之一; 以及垂直振荡器，其具有连接到所述多路复用器的输出端子的输入端子，用于响应于由所述多路复用器选择的所述时钟信号和所述垂直同步信号中选择的一个产生预定频率的垂直振荡信号。

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