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1. 发明授权

US06803893B1 Scan rate controller 失效
标题翻译：扫描速率控制器
公开(公告)号：US06803893B1
公开(公告)日：2004-10-12
申请号：US08992955
申请日：1997-12-18
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G336
CPC分类号： G09G3/3611 , G09G3/3674 , G09G5/008 , G09G5/022 , G09G5/399 , G09G2340/0407 , G09G2340/0435 , G09G2360/02
摘要： A scan rate controller includes a write phase lock loop for generating a write clock signal, a read timing generator for generating a fixed read timing clock signal, and a frame memory for storing a video signal according to the write clock signal from the write phase lock loop and a write timing clock signal from a timing generator, and outputting the video signal according to the read timing clock signal from read timing generator, thereby converting an image size in accordance with various video modes into an image size corresponding to a fixed video mode.
摘要翻译：扫描速率控制器包括用于产生写入时钟信号的写入锁相环，用于产生固定的读取定时时钟信号的读取定时发生器和用于根据来自写入锁相位的写时钟信号存储视频信号的帧存储器循环和来自定时发生器的写定时时钟信号，并且根据来自读定时发生器的读定时时钟信号输出视频信号，从而将根据各种视频模式的图像大小转换为与固定视频模式相对应的图像大小。

2. 发明授权

US06201535B1 Flat panel display apparatus with automatic tracking control 有权
标题翻译：具有自动跟踪控制的平板显示设备
公开(公告)号：US06201535B1
公开(公告)日：2001-03-13
申请号：US09246133
申请日：1999-02-08
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G500
CPC分类号： G09G5/008
摘要： A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a delay circuit for delaying the sampling clock signal, a level converter for converting an analog video signal supplied from the host to have a given digital voltage level, a phase detector for detecting the phase difference between the digital voltage level video signal from the level converter and the sampling clock signal delayed by the delay circuit to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal, a micro-controller for generating the delay data to increase or decrease the delay time of the delay circuit to adjust the phase of the sampling clock signal in response to the output of the comparator, and an analog to digital converter for converting the analog video signal into corresponding digital video signal in response to the delayed sampling clock signal.
摘要翻译：平板显示装置包括：采样时钟发生器，用于产生具有对应于从主机提供的同步信号的频率的采样时钟信号，用于延迟采样时钟信号的延迟电路;电平转换器，用于转换从主机具有给定的数字电压电平，相位检测器，用于检测来自电平转换器的数字电压电平视频信号与由延迟电路延迟的采样时钟信号之间的相位差，以产生相位差数据;比较器，用于比较所述相位差数据具有对应于所述同步信号的延迟数据;微控制器，用于产生所述延迟数据以增加或减少所述延迟电路的延迟时间，以响应于所述延迟电路的输出来调整所述采样时钟信号的相位比较器和用于将模拟视频信号转换成相应的数字视频的模数转换器响应于延迟的采样时钟信号而被点亮。

3. 发明授权

US6160542A Tracking control circuit of a display 有权
标题翻译：跟踪显示器的控制电路
公开(公告)号：US6160542A
公开(公告)日：2000-12-12
申请号：US204345
申请日：1998-12-04
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G3/36 , G09G3/20 , G09G5/00
CPC分类号： G09G5/008
摘要： A display includes: a clock signal generator for generating a first sampling clock signal used for converting an analog video signal supplied from a host to a digital video signal; a tracking control circuit for generating tracking control data corresponding to a tracking adjustment key input; an A/D converter for converting the analog video signal to the digital video signal in synchronism with a second clock signal obtained by delaying the first sampling clock signal according to the tracking control data; a high frequency clock signal generator for generating a high frequency clock signal, and the tracking control circuit measuring the presently delayed time of the second sampling clock signal by means of the high frequency clock signal so as to adjust the delayed time according to the tracking control data.
摘要翻译：显示器包括：时钟信号发生器，用于产生用于将从主机提供的模拟视频信号转换为数字视频信号的第一采样时钟信号; 跟踪控制电路，用于产生对应于跟踪调整键输入的跟踪控制数据; A / D转换器，用于与根据跟踪控制数据延迟第一采样时钟信号而获得的第二时钟信号同步地将模拟视频信号转换成数字视频信号; 用于产生高频时钟信号的高频时钟信号发生器，并且跟踪控制电路借助于高频时钟信号测量第二采样时钟信号的当前延迟时间，以便根据跟踪控制调整延迟时间数据。

4. 发明授权

US5966119A Pseudo-synchronizing signal generator for use in digital image processing apparatus 失效
标题翻译：用于数字图像处理装置的伪同步信号发生器
公开(公告)号：US5966119A
公开(公告)日：1999-10-12
申请号：US759598
申请日：1996-12-05
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： H04N5/06 , G09G5/00 , G09G5/18 , H04N3/227 , H04N5/12 , H04N5/04
CPC分类号： H04N5/123
摘要： A pseudo-synchronizing signal generator for use in a digital image processing apparatus is disclosed. The pseudo-synchronizing signal generation circuit comprising a pulse generating circuit for generating a train of predetermined pulses as being a dot clock oscillation signal for use with a digital image processing apparatus in response to a synchronizing signal input from an external source, a counting controller disposed to input a program data signal for synchronizing the program data signal with a pulse output by the pulse generating circuit and for outputting a program data enable signal, a down counter enabled by the program data enable signal synchronized with the clot clock oscillation signal so as to count down from a preset value, a detector for detecting when the down counting operation of the down counter reaches zero for generating a disable signal to be applied to the down counter and for generating a first pseudo-synchronizing signal, and a multiplexer to selectively outputting, as a second pseudo-synchronizing signal, a selected one of the first pseudo-synchronizing signal and the horizontal synchronizing signal in responsive to the program data signal. As a result, the circuit is able to generate a pseudo-synchronizing signal having a predetermined delay time duration with respect to its inherent synchronizing signal, in synchronization with a train of dot clock oscillation signal, thereby enabling a digital image processing apparatus to perform a positioning of a pictorial image being display on a variable visual monitor.
摘要翻译：公开了一种用于数字图像处理装置的伪同步信号发生器。伪同步信号产生电路包括：脉冲发生电路，用于响应于从外部源输入的同步信号，产生预定脉冲序列作为与数字图像处理装置一起使用的点时钟振荡信号;计数控制器输入用于使程序数据信号与由脉冲发生电路输出的脉冲同步的程序数据信号，并输出程序数据使能信号，通过与凝块时钟振荡信号同步的程序数据使能信号使能的递减计数器，以便从预设值向下计数的检测器，用于检测下降计数器的向下计数操作何时达到零以产生要施加到递减计数器的禁用信号并用于产生第一伪同步信号的检测器，以及多路复用器选择性地输出作为第二伪同步信号，选择第一伪同步信号si 并且响应于程序数据信号的水平同步信号。结果，电路能够与点阵时钟振荡信号同步地产生具有相对于其固有同步信号的预定延迟持续时间的伪同步信号，从而使数字图像处理装置执行在可变的视觉监视器上显示图形图像的定位。

5. 发明授权

US5790112A Oscillation and trigger circuit for vertical synchronizing signal 失效
标题翻译：用于垂直同步信号的振荡和触发电路
公开(公告)号：US5790112A
公开(公告)日：1998-08-04
申请号：US648504
申请日：1996-05-15
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： H03K3/282 , H03K5/13 , H04N5/04 , G09G5/00
CPC分类号： H03K5/13 , H04N5/04
摘要： An oscillation and trigger circuit for a vertical synchronizing signal in a display apparatus, the oscillation and trigger circuit comprising: a pulse generator for generating a single pulse for each active cycle of the vertical synchronizing signal; a first signal detector having an input terminal connected to an output terminal of the pulse generator, for determining a state of no input of the vertical synchronizing signal whose frequency is less than a predetermined frequency and for generating a first predetermined signal indicative of the state; a second signal detector having input terminals connected to respective output terminals of the pulse generator and the first signal detector, for checking a time interval of the vertical synchronizing signal input to the pulse generator so as to output a second predetermined signal when the time interval exceeds a predetermined time period and for outputting the second predetermined signal responsive to the first predetermined signal input from the first signal detector; an input signal detector connected to the first signal detector, for determining an input of the vertical synchronizing signal; a multiplexer having a selection input terminal connected to receive the second predetermined signal output from an output terminal of the second signal detector, for selecting for output one of a first clock signal of a predetermined frequency and the vertical synchronizing signal; and a vertical oscillator having an input terminal connected to an output terminal of the multiplexer, for generating a vertical oscillation signal of a predetermined frequency in response to the selected one of the clock signal and the vertical synchronizing signal selected by the multiplexer.
摘要翻译：一种用于显示装置中的垂直同步信号的振荡和触发电路，所述振荡和触发电路包括：脉冲发生器，用于为所述垂直同步信号的每个有效周期产生单个脉冲; 第一信号检测器，其具有连接到脉冲发生器的输出端的输入端，用于确定频率小于预定频率的垂直同步信号的无输入状态，并产生指示状态的第一预定信号; 第二信号检测器，其具有连接到脉冲发生器和第一信号检测器的相应输出端的输入端，用于检查输入到脉冲发生器的垂直同步信号的时间间隔，以便当时间间隔超过时输出第二预定信号预定时间段，并响应于从第一信号检测器输入的第一预定信号输出第二预定信号; 连接到第一信号检测器的输入信号检测器，用于确定垂直同步信号的输入; 多路复用器，其具有选择输入端，连接用于接收从第二信号检测器的输出端输出的第二预定信号，用于选择输出预定频率的第一时钟信号和垂直同步信号之一; 以及垂直振荡器，其具有连接到所述多路复用器的输出端子的输入端子，用于响应于由所述多路复用器选择的所述时钟信号和所述垂直同步信号中选择的一个产生预定频率的垂直振荡信号。

6. 发明授权

US5736873A Power saving control circuit for a display apparatus 失效
标题翻译：一种用于显示装置的节电控制电路
公开(公告)号：US5736873A
公开(公告)日：1998-04-07
申请号：US444279
申请日：1995-05-18
申请人： Ho-dae Hwang
发明人： Ho-dae Hwang
IPC分类号： H04N5/04 , G06F1/32 , G09G1/00 , G09G1/16 , G09G5/00 , H04N5/63 , H03D13/00
CPC分类号： G06F1/3265 , G06F1/32 , G09G1/16 , G09G1/005 , G09G2330/021 , G09G5/006 , Y02B60/1242 , Y02B60/32
摘要： A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.
摘要翻译：构造为能够应用于各种监视器的监视器的功率控制电路，通过考虑垂直和水平的输入来提供根据监视器的状态的开启，待机，暂停和关闭状态的控制信号在检查监视器的水平和垂直同步信号的当前输入状态之后同步信号，从而有助于根据ASIC的监视器的当前电源状态提供控制信号的电路的实施例。

7. 发明授权

US5818416A Image size adjusting apparatus for a digital display monitor 失效
标题翻译：用于数字显示监视器的图像尺寸调整装置
公开(公告)号：US5818416A
公开(公告)日：1998-10-06
申请号：US887128
申请日：1997-07-02
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G3/36 , G06T3/40 , G09G1/08 , G09G3/20 , G09G5/00 , G09G5/18 , H04N5/66 , H04N9/30
CPC分类号： G09G5/005 , G06T3/4084 , G09G2340/0407 , G09G5/18
摘要： An image size adjusting apparatus for a digital display monitor using a liquid crystal display (LCD) panel includes a frequency multiplier circuit having a programmable divider, and six line memories in which two line memories are designated per each color picture signal line. The adjustment of the horizontal size of the display image can be achieved by changing the amount of sampling data in cooperation with the PLL circuit and the programmable divider. Also, adjustment of the vertical size can be achieved by changing the number of scanning lines such that double scanning is performed during one period of the horizontal synchronization signals, using the line memories. Thus, the apparatus provides for a simplification of adjusting operations of the horizontal and vertical image size of a digital display monitor.
摘要翻译：一种用于使用液晶显示器（LCD）面板的数字显示监视器的图像尺寸调整装置包括具有可编程分频器的倍频器电路和每个彩色图像信号线指定两行存储器的六行存储器。可以通过与PLL电路和可编程分频器配合来改变采样数据量来实现显示图像的水平尺寸的调整。此外，可以通过改变扫描线的数量来实现垂直尺寸的调节，使得使用行存储器在水平同步信号的一个周期期间执行双扫描。因此，该装置提供了对数字显示监视器的水平和垂直图像尺寸的调整操作的简化。

8. 发明授权

US6097437A Format converter 失效
标题翻译：格式转换器
公开(公告)号：US6097437A
公开(公告)日：2000-08-01
申请号：US992954
申请日：1997-12-18
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G5/22 , G09G3/20 , G09G5/00 , H03L7/06 , H04N7/01 , H03L7/00 , H04N3/27 , H04N5/46
CPC分类号： G09G5/005 , G09G2340/0414 , G09G2340/0421 , G09G2360/02 , G09G5/006 , H03L7/06
摘要： A format converter includes: a microcomputer for receiving horizontal and vertical synchronizing signals from a host, determining a video mode, and generating data that indicates the number of dots per a period of a horizontal output signal; a W-PLL and time generator for receiving the data from the microcomputer, and generating a write clock signal; an R-PLL and time generator for receiving the data and the horizontal synchronizing signal respectively generated by the microcomputer and the host, and generating a read clock signal; an AD converting section for sampling an analog picture signal received from the host according to the write clock signal of the W-PLL and time generator, and converting it to a digital picture signal; and a format converting section for storing the picture signal received from the AD converter according to the period of the write clock signal of the W-PLL and time generator, and converting the format of the stored picture signal according to the read clock signal received from the R-PLL and time generator.
摘要翻译：格式转换器包括：微处理器，用于从主机接收水平和垂直同步信号，确定视频模式，以及产生指示水平输出信号每周期的点数的数据; W-PLL和时间发生器，用于从微型计算机接收数据，并产生写入时钟信号; 用于接收由微计算机和主机分别产生的数据和水平同步信号的R-PLL和时间发生器，并产生读时钟信号; AD转换部分，用于根据W-PLL和时间发生器的写时钟信号对从主机接收的模拟图像信号进行采样，并将其转换为数字图像信号; 以及格式转换部分，用于根据W-PLL和时间发生器的写入时钟信号的周期来存储从AD转换器接收的图像信号，并根据接收到的读取时钟信号转换存储的图像信号的格式 R-PLL和时间发生器。

9. 发明授权

US5896177A Device for controlling an aspect ratio in tv-monitor integrated wide screen receiver 失效
标题翻译：用于控制电视监视器集成宽屏幕接收机中的宽高比的设备
公开(公告)号：US5896177A
公开(公告)日：1999-04-20
申请号：US805333
申请日：1997-02-24
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： H04N5/18 , G09G5/00 , H04N5/46 , H04N5/52 , H04N5/66 , H04N7/01 , H04N3/27 , H04N5/445
CPC分类号： H04N7/0122
摘要： A device for controlling an aspect ratio in a TV-computer integrated wide screen receiver, includes an input signal select switch for selecting a television signal double-scanned or a computer monitor signal of a VGA mode, a gain controller for controlling a gain of the signal which is selected by the select switch, a clamp circuit for clamping the signal controlled by the gain controller, an analog/digital converter for converting the signal clamped by the clamp circuit, an aspect ratio conversion device for horizontally and vertically converting the digital signal sampled by the analog/digital converter; and a phase-locked loop connected to the analog/digital converter and the aspect ratio conversion device, for correcting an image distortion by controlling a converting clock speed.
摘要翻译：一种用于控制电视机集成宽屏幕接收机中的宽高比的装置，包括用于选择双扫描的电视信号的输入信号选择开关或VGA模式的计算机监视信号，用于控制VGA模式的增益的增益控制器由选择开关选择的信号，用于钳位由增益控制器控制的信号的钳位电路，用于转换由钳位电路钳位的信号的模拟/数字转换器，用于水平和垂直转换数字信号的宽高比转换装置由模拟/数字转换器采样; 以及连接到模拟/数字转换器和宽高比转换装置的锁相环，用于通过控制转换时钟速度来校正图像失真。

10. 发明授权

US06337682B1 Flat panel display apparatus with automatic coarse control 有权
标题翻译：具有自动粗略控制的平板显示设备
公开(公告)号：US06337682B1
公开(公告)日：2002-01-08
申请号：US09246132
申请日：1999-02-08
申请人： Ho-Dae Hwang
发明人： Ho-Dae Hwang
IPC分类号： G09G500
CPC分类号： G09G5/008 , H03L7/18
摘要： A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a phase detector for detecting the phase difference between the sampling clock signal and the synchronous signal to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal to generate a correction signal, a micro-controller for generating the delay data and for increasing or decreasing the frequency divisional value of the sampling clock generator to adjust the frequency of the sampling clock signal in response to the correction signal, and an analog to digital converter for converting an analog video signal into corresponding digital video signal in response to the sampling clock signal. Preferably, the sampling clock generator includes a phase locked loop (PLL) for adjusting the frequency of the sampling clock signal according to the frequency divisional value from the micro-controller. The phase detector comprises a high frequency clock generator for generating a high frequency clock signal with a higher frequency than that of the sampling clock signal, a counter for counting the high frequency clock signal, a latch for latching the output of the counter, and a flip-flop for enabling or disabling the counter and latch according as the synchronous signal or sampling clock signal is inputted.
摘要翻译：平板显示装置包括：采样时钟发生器，用于产生具有与从主机提供的同步信号相对应的频率的采样时钟信号;相位检测器，用于检测采样时钟信号和同步信号之间的相位差，以产生相位差分数据，用于将相位差数据与对应于同步信号的延迟数据进行比较以产生校正信号的比较器，用于产生延迟数据并用于将采样时钟发生器的分频值增加或减小的微控制器响应于校正信号调整采样时钟信号的频率;以及模数转换器，用于响应于采样时钟信号将模拟视频信号转换成相应的数字视频信号。优选地，采样时钟发生器包括用于根据来自微控制器的分频值调整采样时钟信号的频率的锁相环（PLL）。相位检测器包括：高频时钟发生器，用于产生频率高于采样时钟信号的高频时钟信号，用于计数高频时钟信号的计数器，用于锁存计数器的输出的锁存器;以及触发器用于根据输入同步信号或采样时钟信号启用或禁用计数器和锁存器。

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