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1. 发明授权

US07504900B2 Integrated circuit package including programmable oscillators 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US07504900B2
公开(公告)日：2009-03-17
申请号：US11694624
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F1/04 , H03B5/00 , H03B5/12 , H03B5/24 , H03B5/36
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

2. 发明授权

US07382181B2 Method and apparatus for tuning GMC filter 有权
标题翻译： GMC滤波器调谐方法及装置
公开(公告)号：US07382181B2
公开(公告)日：2008-06-03
申请号：US11623686
申请日：2007-01-16
申请人： Golam R. Chowdhury , Douglas R. Holberg
发明人： Golam R. Chowdhury , Douglas R. Holberg
IPC分类号： H03K5/00
CPC分类号： H03H11/04 , H03B5/14 , H03F1/342 , H03F3/45183 , H03F2203/45318 , H03F2203/45366 , H03L7/0995
摘要： A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.
摘要翻译：公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。滤波器的输入使振荡频率调谐到预定频率。

3. 发明授权

US07323855B2 Digital pulse width modulated power supply with variable LSB 失效
标题翻译：数字脉宽调制电源，可变LSB
公开(公告)号：US07323855B2
公开(公告)日：2008-01-29
申请号：US11095844
申请日：2005-03-31
申请人： Jinwen Xiao , Ka Y. Leung , Douglas R. Holberg
发明人： Jinwen Xiao , Ka Y. Leung , Douglas R. Holberg
IPC分类号： G05F1/46 , G05F1/62
CPC分类号： H02M3/33515 , H02M3/33576 , H02M2001/0012
摘要： A DC-DC digital pulse width modulated power supply is disclosed for generating a DC regulated output voltage. A digital control node has a digital control voltage disposed thereon for controlling the operation of the supply, wherein the digital control voltage has a substantially zero voltage when the output voltage of the supply is at a desired regulation, the digital control voltage having a resolution defined by a least significant bit (LSB). An input node receives a DC analog reference voltage defining the output voltage of the supply. A difference device determines the difference between the analog reference voltage and the output voltage to generate said digital control voltage. An LSB variation device varies the size of the LSB without varying the value of the digital control voltage for a substantially zero difference between the analog reference voltage and the output voltage.
摘要翻译：公开了用于产生直流调节输出电压的DC-DC数字脉宽调制电源。数字控制节点具有设置在其上用于控制电源的操作的数字控制电压，其中当电源的输出电压处于期望的调节时，数字控制电压具有基本为零的电压，数字控制电压具有定义的分辨率通过最低有效位（LSB）。输入节点接收限定电源的输出电压的DC模拟参考电压。差分装置确定模拟参考电压和输出电压之间的差异，以产生所述数字控制电压。 LSB变化装置改变LSB的大小，而不改变模拟参考电压和输出电压之间的基本上零差的数字控制电压的值。

4. 发明授权

US07304679B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US07304679B1
公开(公告)日：2007-12-04
申请号：US10742170
申请日：2003-12-19
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5/222 , H04N5/235 , H04N5/20 , H03M1/12
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

5. 发明授权

US06891487B2 Capacitor calibration in SAR converter 有权
标题翻译： SAR转换器中的电容校准
公开(公告)号：US06891487B2
公开(公告)日：2005-05-10
申请号：US10752913
申请日：2004-01-07
申请人： Ka Y. Leung , Douglas R. Holberg , Kafai Leung
发明人： Ka Y. Leung , Douglas R. Holberg , Kafai Leung
IPC分类号： G06F13/28 , H01C10/16 , H03M1/06 , H03M1/10 , H03M1/12 , H03M1/34 , H03M1/38 , H03M1/46 , H03M1/66 , H03M1/78
CPC分类号： H03M1/1057 , H03M1/468
摘要： Capacitor calibration in SAR converter. A method for calibrating a switched capacitor array in a SAR data converter is disclosed, which array includes a plurality of primary capacitors having a common node plate interfaced to a common node and a switched plate interfaced to a switch that is operable to be switched between first and second reference voltages. A comparator having an input connected to the common node and a reference input connected to a comparator reference node receives a comparator reference voltage. In a first calibration step for calibrating one of the primary capacitors, a reference capacitor is provided and then, the switched plate of the select primary capacitor is connected to the first reference voltage, the switched plate of the other capacitors and the reference capacitor are connected to the second reference voltage, and the common node and the comparator reference node are driven with a driver to dispose a first voltage thereon. In a second calibration step, the common node is allowed to float, the switched plate of the select primary capacitor is connected to the second reference voltage, the switched plate of the reference capacitor is connected to the first reference voltage, and the voltage on the common node is compared to the first voltage on the comparator reference node. A determination is then made as to whether the voltage on the common node is greater than the first voltage. A plurality of trim capacitors are provided and, if in the second calibration step, the voltage on the common node was determined to be greater than the first voltage, then one of the trim capacitors is disposed in parallel with the select one of the primary capacitors and then the first and second calibrating steps are repeated.
摘要翻译： SAR转换器中的电容校准。公开了一种用于校准SAR数据转换器中的开关电容器阵列的方法，该阵列包括具有与公共节点接口的公共节点板的多个初级电容器和与开关接口的开关板，该开关板可操作以在第一和第二参考电压。具有连接到公共节点的输入和连接到比较器参考节点的参考输入的比较器接收比较器参考电压。在用于校准主电容器之一的第一校准步骤中，提供参考电容器，然后，选择一次电容器的开关板连接到第一参考电压，另一电容器的开关板和参考电容器连接到第二参考电压，并且公共节点和比较器参考节点由驱动器驱动以在其上设置第一电压。在第二校准步骤中，允许公共节点浮动，选择主电容器的开关板连接到第二参考电压，参考电容器的开关板连接到第一参考电压，并且在公共节点与比较器参考节点上的第一个电压进行比较。然后确定公共节点上的电压是否大于第一电压。提供多个修整电容器，如果在第二校准步骤中，将公共节点上的电压确定为大于第一电压，则将一个修整电容器与主电容器中的选择一个平行设置然后重复第一和第二校准步骤。

6. 发明授权

US06400300B1 D/A converter street effect compensation 有权
标题翻译： D / A转换器街道效应补偿
公开(公告)号：US06400300B1
公开(公告)日：2002-06-04
申请号：US09584311
申请日：2000-05-31
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M178
CPC分类号： H03M1/0678 , H03M1/682 , H03M1/765 , H04J14/0226 , H04L12/2856 , H04Q11/0067 , H04Q11/0071
摘要： A digital-to-analog converter (DAC) employs a main DAC resistor string and a sub-resistor string formed in a semiconductor material. A main DAC conversion circuit is formed with a headroom resistor in series with the main DAC resistor string. The headroom resistor provides an operating voltage for current drivers in the sub-resistor string. The headroom resistor is formed adjacent to the main DAC resistor string in the semiconductor material to provide street effect compensation thereto. In practice, the main DAC resistor string is formed as two sets of resistor strings. The headroom resistor is formed as a first resistor string adjacent one main DAC resistor string set, and as a second resistor string adjacent the other main DAC resistor string set. The plural resistors of the headroom resistor strings have resistor values equal to the plural resistors of the respective main DAC resistor string sets.
摘要翻译：数模转换器（DAC）采用主DAC电阻串和形成在半导体材料中的子电阻串。主DAC转换电路形成有与主DAC电阻串串联的裕量电阻器。裕量电阻为子电阻串中的电流驱动器提供工作电压。余量电阻器形成在半导体材料中与主DAC电阻串相邻以提供街道效应补偿。实际上，主DAC电阻串形成两组电阻串。余量电阻器形成为与一个主DAC电阻串组相邻的第一电阻器串，并且形成为与另一个主DAC电阻串组相邻的第二电阻器串。裕量电阻串的多个电阻器具有等于相应的主DAC电阻串组的多个电阻器的电阻值。

7. 发明申请

US20080079148A1 PACKAGE FOR MIXED SIGNAL MCU WITH MINIMAL PIN COUNT 审中-公开
标题翻译：具有最小引脚数的混合信号MCU的封装
公开(公告)号：US20080079148A1
公开(公告)日：2008-04-03
申请号：US11537631
申请日：2006-09-30
申请人： KA Y. LEUNG , JOHN M. CZARNOWSKI , DOUGLAS R. HOLBERG , MATTHEW WEST , ROSS TODD BANNATYNE
发明人： KA Y. LEUNG , JOHN M. CZARNOWSKI , DOUGLAS R. HOLBERG , MATTHEW WEST , ROSS TODD BANNATYNE
IPC分类号： H01L23/48
CPC分类号： H01L23/5382 , G06F1/22 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A minimal pin package for a mixed signal integrated circuit for a mixed signal processor based integrated circuit includes a semiconductor chip having a plurality of bond pads disposed thereon with a digital processor digitally interfaceable with at least one of the bond pads. An analog circuit block is provided and interfaceable with at least one of the bond pads. A die pad is provided on which the chip is mounted and N terminals on the package are interfaced to the exterior of the package, one of which is integral with the die pad. Bond wires interface select ones of the bond pads to a supply designated one of the terminals, a ground one of the terminals and the die pad associated with one of the terminals, the rest of the N-3 terminals interfaced to remaining functionality of the chip.
摘要翻译：用于基于混合信号处理器的集成电路的混合信号集成电路的最小引脚封装包括半导体芯片，其具有设置在其上的多个接合焊盘，数字处理器可与至少一个接合焊盘数字地接口。提供模拟电路块并与至少一个接合焊盘接口。芯片安装在芯片上，封装上的N个端子连接到封装的外部，其中一个与管芯焊盘成一体。接合线接口将一个接合焊盘选择为指定为一个端子的电源，接地端子和与一个端子相关联的管芯焊盘，其余的N-3端子与芯片的剩余功能相连接。

8. 发明授权

US07256611B2 Cross-bar matrix with LCD functionality 失效
标题翻译：带有LCD功能的横杆矩阵
公开(公告)号：US07256611B2
公开(公告)日：2007-08-14
申请号：US11005700
申请日：2004-12-07
申请人： Douglas R. Holberg , Kenneth W. Fernald
发明人： Douglas R. Holberg , Kenneth W. Fernald
IPC分类号： H03K19/177
CPC分类号： H03K19/1731
摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.
摘要翻译：交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个单元由控制输入。

9. 发明授权

US06879004B2 High voltage difference amplifier with spark gap ESD protection 有权
标题翻译：高电压差放大器具有火花隙ESD保护
公开(公告)号：US06879004B2
公开(公告)日：2005-04-12
申请号：US10288188
申请日：2002-11-05
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A spark gap device for protecting an integrated circuit. The spark gap device includes a first node for receiving an input signal and a second node to be protected. A first conductive layer is conductively interfaced to the first node and the second node and disposed therebetween. A second conductive layer is connected to a sink voltage and separated from the first conductive layer by an insulating layer of a predetermined thickness. A portion of the first conductive layer is disposed proximate to the second conductive layer and not overlying the second conductive layer, such that a gap is formed therebetween and the gap having a dimension that is greater than the thickness of the insulating layer.
摘要翻译：一种用于保护集成电路的火花隙装置。火花隙装置包括用于接收输入信号的第一节点和待保护的第二节点。第一导电层导电地接合到第一节点和第二节点并且设置在它们之间。第二导电层连接到宿电压，并通过预定厚度的绝缘层与第一导电层分离。第一导电层的一部分设置成靠近第二导电层并且不覆盖第二导电层，使得在其间形成间隙，并且间隙的尺寸大于绝缘层的厚度。

10. 发明授权

US06724336B2 Segmented D/A converter with enhanced dynamic range 失效
标题翻译：具有增强动态范围的分段D / A转换器
公开(公告)号：US06724336B2
公开(公告)日：2004-04-20
申请号：US10141462
申请日：2002-05-07
申请人： Ka Y. Leung , Douglas R. Holberg
发明人： Ka Y. Leung , Douglas R. Holberg
IPC分类号： H03M166
CPC分类号： H03M1/0602 , H03M1/682 , H03M1/765
摘要： A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.
摘要翻译：具有串联连接的晶体管的数模转换器形成用于各个分段电阻串的高阻抗电流源。形成用于一个电阻器串的电流吸收器的串联晶体管通过利用负反馈放大器呈现高输出阻抗。通过使用适当的增益电阻配置输出放大器，可以消除一个电阻串中的裕量电阻和偏移电阻的影响。通过使用相同值的主电阻和子电阻串的所有电阻，可以实现高精度的D / A转换。

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