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1. 发明授权

US06734860B1 Apparatus for providing videodriving capability from various types of DACS 有权
标题翻译：用于从各种类型的DACS提供视频传输能力的设备
公开(公告)号：US06734860B1
公开(公告)日：2004-05-11
申请号：US09632447
申请日：2000-08-04
申请人： Michael Potter , Clifford A. Whitmore
发明人： Michael Potter , Clifford A. Whitmore
IPC分类号： G06F1500
CPC分类号： G09G5/395
摘要： An apparatus for processing a graphical data stream for display on a display device includes a processor, a first conversion module and a second conversion module. The processor determines the characteristics of the graphical data stream. The first conversion module and the second conversion module convert the graphical data stream in a first format to a second format. The graphical data stream is directed to the first conversion module by a first data path and the graphical data stream is directed to the second conversion module by a second data path. A switching system is used to alternately connect the first conversion module through the first data path and the second conversion module through the second data path.
摘要翻译：用于处理用于在显示装置上显示的图形数据流的装置包括处理器，第一转换模块和第二转换模块。处理器确定图形数据流的特性。第一转换模块和第二转换模块将第一格式的图形数据流转换成第二格式。图形数据流通过第一数据路径被引导到第一转换模块，并且图形数据流通过第二数据路径被引导到第二转换模块。交换系统用于通过第一数据路径和第二转换模块通过第二数据路径交替地连接第一转换模块。

2. 发明授权

US06642928B1 Multi-processor graphics accelerator 有权
标题翻译：多处理器图形加速器
公开(公告)号：US06642928B1
公开(公告)日：2003-11-04
申请号：US10136505
申请日：2002-05-01
申请人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
发明人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
IPC分类号： G06F1516
CPC分类号： G06T15/005 , G06T1/20 , G09G5/393 , G09G5/395
摘要： An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.
摘要翻译：一种用于在具有多个像素的水平扫描显示装置上显示多边形的装置包括：第一和第二光栅化器，其每个处理相应的第一和第二组像素。每组像素包括横向于显示器的水平扫描的垂直条纹。为此，第一光栅化器具有用于接收与多边形有关的多边形数据的输入。第一光栅化器确定要被点亮以显示多边形的第一组像素，并且还确定第一组像素的显示特性。类似的方式，第二光栅化器还包括用于接收与多边形有关的多边形数据的输入。第二光栅化器类似地确定要被点亮以显示多边形的第二组像素，并且还确定第二组像素的显示特性。第一和第二组像素没有公共像素，并且是显示装置上横向于水平扫描方向的像素的垂直条纹。

3. 发明授权

US06667744B2 High speed video frame buffer 有权
公开(公告)号：US06667744B2
公开(公告)日：2003-12-23
申请号：US09934444
申请日：2001-08-21
申请人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
发明人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
IPC分类号： G06F1516
CPC分类号： G09G5/39 , G09G5/363 , G09G5/393 , G09G2360/12 , G09G2360/121 , G09G2360/122 , G11C7/1015 , G11C7/1018 , G11C8/00
摘要： A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.

4. 发明授权

US07616200B1 System for reducing aliasing on a display device 有权
标题翻译：用于减少显示设备上的混叠的系统
公开(公告)号：US07616200B1
公开(公告)日：2009-11-10
申请号：US09329557
申请日：1999-06-10
申请人： Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore , James L. Deming , Stewart G. Carlton , Matt E. Buckelew , Dale L. Kirkland , Timothy S. Johnson
发明人： Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore , James L. Deming , Stewart G. Carlton , Matt E. Buckelew , Dale L. Kirkland , Timothy S. Johnson
IPC分类号： G06T15/00
CPC分类号： G06T11/001
摘要： An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique location on the display device. Each sample pattern has at least one sample location. It then is determined if the first image intersects any of the sample locations on each pixel. Pixels determined to have at least one sample location that intersect the first image thus are illuminated.
摘要翻译：在具有多个像素的显示装置上显示第一图像的装置和方法将多个样本图案中的一个分配给显示装置上的每个像素。基于其在显示设备上的唯一位置，为每个像素分配多个图案中的一个。每个样品图案至少有一个样品位置。然后确定第一图像是否与每个像素上的任何样本位置相交。确定具有与第一图像相交的至少一个采样位置的像素被照亮。

5. 发明授权

US06628288B1 Selectable back end unit 有权
标题翻译：可选后端设备
公开(公告)号：US06628288B1
公开(公告)日：2003-09-30
申请号：US09633092
申请日：2000-08-04
申请人： Michael Potter , Clifford A. Whitmore , Jeff S. Ford
发明人： Michael Potter , Clifford A. Whitmore , Jeff S. Ford
IPC分类号： G06F1516
CPC分类号： G09G5/363 , G09G5/08 , G09G2320/0276
摘要： A back end unit for use with a graphics processor includes an input for receiving graphics data streams from the graphics processor, an output for transmitting graphics data streams, and a plurality of paths, coupled with the input and output, that direct graphics data streams between the input and the output. The plurality of paths direct data between the various modules that are a part of the back end unit. To that end, among other things, the back end unit also includes a gamma correction module that applies gamma correction operations to graphics data streams, a cursor module that adds cursor data to graphics data streams, and a digital to analog converter that converts the graphics data streams from a digital format to an analog format. The plurality of paths thus permit graphics data streams to pass through no more than two of the gamma correction module, the cursor module, and the digital to analog converter.
摘要翻译：用于图形处理器的后端单元包括用于从图形处理器接收图形数据流的输入，用于传输图形数据流的输出以及与输入和输出耦合的多个路径，其将图形数据流之间引导输入和输出。多个路径在作为后端单元的一部分的各个模块之间引导数据。为此，后端单元还包括对图形数据流应用伽马校正操作的伽马校正模块，将图形数据流添加光标数据的光标模块以及转换图形的数模转换器从数字格式到模拟格式的数据流。因此，多个路径允许图形数据流通过不超过两个伽马校正模块，光标模块和数模转换器。

6. 发明授权

US06535216B1 Multi-processor graphics accelerator 有权
公开(公告)号：US06535216B1
公开(公告)日：2003-03-18
申请号：US10136585
申请日：2002-05-01
申请人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
发明人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
IPC分类号： G06F1516
CPC分类号： G06T15/005 , G06T1/20 , G09G5/393 , G09G5/395
摘要： An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.

7. 发明授权

US06278645B1 High speed video frame buffer 有权
标题翻译：高速视频帧缓冲
公开(公告)号：US06278645B1
公开(公告)日：2001-08-21
申请号：US09129293
申请日：1998-08-05
申请人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
发明人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
IPC分类号： G09G116
CPC分类号： G09G5/39 , G09G5/363 , G09G5/393 , G09G2360/12 , G09G2360/121 , G09G2360/122 , G11C7/1015 , G11C7/1018 , G11C8/00
摘要： A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.
摘要翻译：用于存储用于在显示器上显示图形图像的像素信息的设备包括帧缓冲器和处理器。该信息包括强度值和与每个像素的多个附加平面中的每一个相关联的值。帧缓冲存储器具有一系列用于存储要输出到显示器的信息的连续地址。帧缓冲器可以被细分为多个块，其中每个块对应于具有多个连续像素的显示区域。处理器将像素信息放置在帧缓冲存储器内，使得在给定块中，将连续地址的第一集合放置在块中的每个像素的强度值。

8. 发明授权

US5864512A High-speed video frame buffer using single port memory chips 失效
标题翻译：高速视频帧缓冲器采用单端口存储芯片
公开(公告)号：US5864512A
公开(公告)日：1999-01-26
申请号：US832708
申请日：1997-04-11
申请人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
发明人： Matt E. Buckelew , Stewart G. Carlton , James L. Deming , Michael S. Farmer , Steven J. Heinrich , Mark A. Mosley , Clifford A. Whitmore
IPC分类号： G09G5/02 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395 , G09G5/399 , G11C7/10 , G11C8/00 , G11C13/00
CPC分类号： G09G5/363 , G09G5/39 , G09G5/393 , G09G5/395 , G11C7/1015 , G11C7/1018 , G11C8/00 , G11C8/04 , G09G2360/12 , G09G2360/121 , G09G2360/123 , G09G2360/128 , G09G5/022 , G09G5/399
摘要： This invention relates to providing high-speed video graphics through use of single ported memory chips on the video card.
摘要翻译：本发明涉及通过在视频卡上使用单端口存储芯片来提供高速视频图形。

9. 发明授权

US06476816B1 Multi-processor graphics accelerator 有权
标题翻译：多处理器图形加速器
公开(公告)号：US06476816B1
公开(公告)日：2002-11-05
申请号：US09353495
申请日：1999-07-15
申请人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
发明人： James L. Deming , Matt E. Buckelew , Clifford A. Whitmore , Steven J. Heinrich , Dale L. Kirkland , Timothy S. Johnson
IPC分类号： G06F1516
CPC分类号： G06T15/005 , G06T1/20 , G09G5/393 , G09G5/395
摘要： An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.
摘要翻译：一种用于在具有多个像素的水平扫描显示装置上显示多边形的装置包括：第一和第二光栅化器，其每个处理相应的第一和第二组像素。每组像素包括横向于显示器的水平扫描的垂直条纹。为此，第一光栅化器具有用于接收与多边形有关的多边形数据的输入。第一光栅化器确定要被点亮以显示多边形的第一组像素，并且还确定第一组像素的显示特性。以类似的方式，第二光栅化器还包括用于接收与多边形有关的多边形数据的输入。第二光栅化器类似地确定要被点亮以显示多边形的第二组像素，并且还确定第二组像素的显示特性。第一和第二组像素没有公共像素，并且是显示装置上横向于水平扫描方向的像素的垂直条纹。

10. 发明授权

US6157393A Apparatus and method of directing graphical data to a display device 有权
标题翻译：将图形数据引导到显示装置的装置和方法
公开(公告)号：US6157393A
公开(公告)日：2000-12-05
申请号：US354462
申请日：1999-07-15
申请人： Michael Potter , Clifford A. Whitmore
发明人： Michael Potter , Clifford A. Whitmore
IPC分类号： G06T1/20 , G09G5/393 , G09G5/395 , G06F15/80
CPC分类号： G06T1/20 , G09G5/395 , G09G5/393
摘要： An apparatus for and method of directing graphical data toward a display device from a plurality of graphics processors couples the graphics processors in a manner that reduces the size of the interface on each graphics processor. In particular, each graphics processor produces graphical data for an associated set of pixels on the display device, where each pixel is represented by a first amount of graphical data. The graphics processors are arranged so that one of the graphics processors is a destination processor. The total number of graphics processors that are not designated as the destination processor thus constitute a remaining number. Each graphics processor produces a second amount of graphical data during each clock cycle of a common clock. The first amount of graphical data, however, is comprised of at least substantially two times the second amount of graphical data. The graphics processors then are coupled so that during each clock cycle, the destination processor receives no more graphical data from the other processors than an amount equal to the product of the remaining number and the second amount.
摘要翻译：从多个图形处理器向显示设备引导图形数据的装置和方法以降低每个图形处理器上的接口的大小的方式来耦合图形处理器。特别地，每个图形处理器产生显示设备上相关联的像素集合的图形数据，其中每个像素由第一数量的图形数据表示。图形处理器被布置成使得一个图形处理器是目的地处理器。因此，未指定为目标处理器的图形处理器的总数构成剩余数。每个图形处理器在公共时钟的每个时钟周期期间产生第二数量的图形数据。然而，第一数量的图形数据由至少基本上是第二数量的图形数据的两倍组成。然后，图形处理器被耦合，使得在每个时钟周期期间，目的地处理器不再接收来自其他处理器的图形数据，而不是等于剩余数量和第二量的乘积的量。

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