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1. 发明授权

US5656834A IC standard cell designed with embedded capacitors 失效
标题翻译： IC标配电池设计嵌入式电容器
公开(公告)号：US5656834A
公开(公告)日：1997-08-12
申请号：US662742
申请日：1996-06-10
申请人： Claus D. Grzyb , Ori K. Mizrahi-Shalom
发明人： Claus D. Grzyb , Ori K. Mizrahi-Shalom
IPC分类号： H01L27/02 , H01L29/78 , H01L27/10
CPC分类号： H01L27/0207 , H01L27/0218
摘要： Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). To reduce RFI, on-chip dedoupling capacitors are included in the design. To gain maximum advantage of these decoupling capacitors, they should be placed close to drivers and flip-flops. In a standard cell design approach for fabrication of the ICs, capacitors are embedded below the power supply lines. These capacitors are put in special cells, called cap-cells, which are placed by the place and route software on either side of each row of standard cells. Thin oxide capacitors are preferred because they offer the largest capacitance per area. In addition, first and second metal above the capacitor are increased to form thick oxide capacitors that give additional capacitance.
摘要翻译：高频运行的集成电路是RFI（射频干扰）的潜在来源。为了减少RFI，设计中包括片上去耦电容。为了获得这些去耦电容器的最大优势，它们应放置在靠近驱动器和触发器的位置。在用于制造IC的标准电池设计方法中，电容器嵌入在电源线之下。这些电容器被放入被称为cap-cell的特殊单元格中，这些单元被放置在每一行标准单元两侧的位置和路径软件中。薄氧化物电容器是优选的，因为它们提供每面积最大的电容。此外，电容器上方的第一和第二金属增加以形成赋予额外电容的厚氧化物电容器。

2. 发明授权

US4862404A Digital circuit for suppressing fast signal variations 失效
标题翻译：用于抑制快速信号变化的数字电路
公开(公告)号：US4862404A
公开(公告)日：1989-08-29
申请号：US71695
申请日：1987-07-09
申请人： Wolfgang Schwartz , Otto L. Warmuth , Claus D. Grzyb
发明人： Wolfgang Schwartz , Otto L. Warmuth , Claus D. Grzyb
IPC分类号： H03K5/1252 , G06F7/66 , H03H17/02 , H04B10/60 , H04L25/03 , H04L25/08 , H04Q9/00
CPC分类号： H04B10/60 , G06F7/66 , H03H17/02
摘要： A digital circuit which receives a serial input signal and which suppresses fast signal variations. The digital circuit includes an integrator circuit (1) which generates a multi-bit signal by integration of the serial input signal. The output signal of the integrator circuit is applied to an evaluation circuit (2) which generates a serial output signal which assumes a first state when the multi-bit signal exceeds a first threshold value and a second state when the multi-bit signal is below a second threshold value.
摘要翻译：接收串行输入信号并抑制快速信号变化的数字电路。数字电路包括积分器电路（1），其通过串行输入信号的积分产生多位信号。积分器电路的输出信号被施加到评估电路（2），其产生当多位信号超过第一阈值时呈现第一状态的串行输出信号，并且当多位信号低于多位信号时，产生第二状态第二阈值。

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