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    • 6. 发明申请
    • PAPER SHREDDING TOOL
    • 纸制工具
    • US20090014566A1
    • 2009-01-15
    • US11776344
    • 2007-07-11
    • King Biu MAKChung Ming MAKRonald Chung Yin MAK
    • King Biu MAKChung Ming MAKRonald Chung Yin MAK
    • B02C1/08
    • B02C18/0007
    • A paper shredding tool is disclosed as including a first pair of cutters partly abutting each other along a first cutting plane; a second pair of cutters adjacent to the first pair of cutters, the second pair of cutters partly abutting each other along a second cutting plane; a third pair of cutters partly abutting each other along a third cutting plane; and a fourth pair of cutters adjacent to the third pair of cutters, the fourth pair of cutters partly abutting each other along a fourth cutting plane; in which each pair of cutters are rotatable relative to each other to cut a piece of paper passing between the pair of cutters along their respective cutting plane; and the distance between the first cutting plane and the second cutting plane is different from the distance between the third cutting plane and the fourth cutting plane.
    • 公开了一种切碎工具,其包括沿着第一切割平面彼此部分地邻接的第一对切割器; 与所述第一对切割器相邻的第二对切割器,所述第二对切割器沿着第二切割平面彼此部分地邻接; 第三对切割器沿着第三切割平面彼此部分地邻接; 以及与所述第三对切割器相邻的第四对切割器,所述第四对切割器沿着第四切割平面彼此部分地邻接; 其中每对切割器可相对于彼此旋转以沿着它们各自的切割平面切割通过所述一对切割器之间的一张纸; 并且第一切割平面与第二切割平面之间的距离与第三切割平面与第四切割平面之间的距离不同。
    • 8. 发明申请
    • De-interleaver for data decoding
    • 去交织器用于数据解码
    • US20070115960A1
    • 2007-05-24
    • US11267752
    • 2005-11-04
    • Shih-Chung Yin
    • Shih-Chung Yin
    • H04L12/56
    • H04L1/0045H04L1/0059H04L1/0071H04L27/2601
    • A de-interleaver for data decoding. Two memory banks are configured to store data in column order and output the data in row order. A de-interleaving encoder receives a stream of interleaved data values, generates an input address for both the two memory banks contingent upon a modulation mode and based on a count value, and sequentially writes the interleaved data values to either of the memory banks according to the input address. Additionally, a de-interleaving decoder generates respective output addresses for the two memory banks based on a second count value and contingent upon the modulation mode, and a dummy insertion indicator. The de-interleaving decoder reads the interleaved data values from the two memory banks according to the respective output address, and extracts decision metrics from the read data according to relevant output indicators.
    • 用于数据解码的解交织器。 两个存储体被配置为以列顺序存储数据,并以行顺序输出数据。 解交织编码器接收交织数据流的流,根据调制模式生成两个存储体两者的输入地址,并根据计数值,依次按顺序将交错数据值写入存储体 输入地址。 此外,解交织解码器基于第二计数值并且根据调制模式生成两个存储体的相应输出地址,以及虚拟插入指示符。 解交织解码器根据相应的输出地址从两个存储体读取交织的数据值,并根据相关的输出指示符从读取的数据中提取决策度量。
    • 9. 发明申请
    • Low power module for a station of a wireless communication system and related method
    • 用于无线通信系统站的低功率模块及相关方法
    • US20070076683A1
    • 2007-04-05
    • US11241743
    • 2005-09-30
    • Ching ChungShih-Chung Yin
    • Ching ChungShih-Chung Yin
    • H04J3/06
    • H04W52/0216H04W52/0293Y02D70/142
    • The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX) The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
    • 本发明涉及一种低功率模块,特别涉及应用于无线通信系统的站中的低功率模块。 低功率模块包括第一MAC模块,第二MAC模块,低功率开关寄存器,控制寄存器单元,慢时钟发生器和多路复用器(MUX)。第一和第二MAC模块以正常的方式发送和接收分组 操作模式和省电模式。 低功率开关寄存器将当前模式切换到另一种模式。 控制寄存器单元在低功率开关寄存器的控制下控制RF / BB模块和时钟发生器。 在省电模式下,慢时钟发生器为第二个MAC模块生成一个缓慢的工作时钟。 MUX根据控制寄存器单元周期性地选择正常操作或慢操作时钟作为第二MAC模块的时钟。