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1. 发明授权

US07117426B2 Branch metric computation and add-compare-select operation in viterbi decoders 有权
标题翻译：维特比解码器中的分支度量计算和加法比较选择操作
公开(公告)号：US07117426B2
公开(公告)日：2006-10-03
申请号：US10724655
申请日：2003-12-01
申请人： Kuo-Ming Wu , Shih-Chung Yin
发明人： Kuo-Ming Wu , Shih-Chung Yin
IPC分类号： H03M13/03
CPC分类号： H03M13/6362 , H03M13/3961 , H03M13/4107 , H03M13/4192 , H03M13/6502
摘要： An apparatus for branch metric computation and add-compare-select operation in a rate 1/n Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a measure between a currently received data symbol and a corresponding branch label. The add-compare-select unit can generate respective decision bits for a pair of odd and even states at next instant with a novel pre-computational architecture. Further, a local winner between the odd and even states is predetermined in a manner providing reduction of the activity required by the computation. Thus the add-compare-select unit outputs a path metric of the local winner, whereby a saving of half the output number of path metrics is achieved.
摘要翻译：一种用于具有约束长度为K的速率1 / n维特比解码器中的分支度量计算和加法比较选择操作的装置。本发明的装置包括分支度量发生器和加法比较选择单元。分支度量生成器计算多个分支度量，每个分支度量是当前接收的数据符号和对应的分支标签之间的度量。加法比较选择单元可以在下一个瞬间通过新颖的预计算架构来产生一对奇偶数状态的各自的决定位。此外，奇数和偶数状态之间的本地胜利者以提供计算所需的活动减少的方式被预先确定。因此，加法比较选择单元输出本地获胜者的路径度量，从而实现路径度量的输出数量的一半的保存。

2. 发明申请

US20100304780A1 Low Power Module for a Station of a Wireless Communication System and Related Method 有权
标题翻译：一种无线通信系统站的低功耗模块及相关方法
公开(公告)号：US20100304780A1
公开(公告)日：2010-12-02
申请号：US12820403
申请日：2010-06-22
申请人： Ching An Chung , Shih-Chung Yin
发明人： Ching An Chung , Shih-Chung Yin
IPC分类号： H04B7/00
CPC分类号： H04W52/0216 , H04W52/0293 , Y02D70/142
摘要： The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
摘要翻译：本发明涉及一种低功率模块，特别涉及应用于无线通信系统的站中的低功率模块。低功率模块包括第一MAC模块，第二MAC模块，低功率开关寄存器，控制寄存器单元，慢时钟发生器和多路复用器（MUX）。第一和第二MAC模块分别以正常操作模式和省电模式发送和接收分组。低功率开关寄存器将当前模式切换到另一种模式。控制寄存器单元在低功率开关寄存器的控制下控制RF / BB模块和时钟发生器。在省电模式下，慢时钟发生器为第二个MAC模块生成一个缓慢的工作时钟。 MUX根据控制寄存器单元周期性地选择正常操作或慢操作时钟作为第二MAC模块的时钟。

3. 发明授权

US07496159B2 Survivor memory management in a Viterbi decoder 失效
标题翻译：维特比解码器中的幸存者内存管理
公开(公告)号：US07496159B2
公开(公告)日：2009-02-24
申请号：US10724915
申请日：2003-12-01
申请人： Kuo-Ming Wu , Shih-Chung Yin
发明人： Kuo-Ming Wu , Shih-Chung Yin
IPC分类号： H03D1/00
CPC分类号： H03M13/6362 , H03M13/4192 , H03M13/6502
摘要： An apparatus for survivor path decoding in a Viterbi decoder with a constraint length of K. The apparatus of the invention includes a best survivor unit, a a register-exchange network, and a trace-back unit. The best survivor unit receives path metrics of 2K−2 local winner states from which a best state is selected every L iterations. Meanwhile, the register-exchange network generates decision vectors of survivor paths leading to 2K−1 states at instant i according to decision bits of all states from instant i−L to instant i. Every L iterations the register-exchange network outputs L-bit decision vectors for all states at instant i. Then the trace-back unit stores the decision vectors and finds a global survivor path sequence by following the decision vectors back from the best state at instant i−L. In this manner, L decoded bits can be output from the trace-back unit every L iterations.
摘要翻译：一种具有约束长度为K的维特比解码器中的幸存路径解码装置。本发明的装置包括最佳幸存器单元，寄存器交换网络和追溯单元。最好的幸存者单位接收2K-2局部优胜者状态的路径度量，每L次迭代选择最佳状态。同时，寄存器交换网络根据从即时i-L到瞬时i的所有状态的判定位，产生在时刻i导致2K-1状态的幸存路径的判定向量。每个L迭代，寄存器交换网络在时刻i输出所有状态的L位决策向量。然后，追溯单元存储决策向量，并且通过从时刻i-L处的最佳状态返回的判定向量来查找全局幸存路径序列。以这种方式，每L次迭代可以从追溯单元输出L个解码的比特。

4. 发明申请

US20080031386A1 Method and device for robust signal detection in wireless communications 审中-公开
标题翻译：无线通信中鲁棒信号检测的方法和装置
公开(公告)号：US20080031386A1
公开(公告)日：2008-02-07
申请号：US11498432
申请日：2006-08-02
申请人： Shang-Ho Tsai , Chung-Yen Huang , Shih-Chung Yin
发明人： Shang-Ho Tsai , Chung-Yen Huang , Shih-Chung Yin
IPC分类号： H04L27/06
CPC分类号： G01S7/021
摘要： A method, algorithm, architecture, circuits, and/or systems for robust radar signal detection for wireless communications are disclosed. In one embodiment, a method of detecting a predefined signal pulse event in a wireless network device can include the steps of: (i) comparing a power of a received signal pulse to a predetermined power threshold of a predefined signal; (ii) determining a duration of the received signal pulse when the power of the received signal pulse is greater than the predetermined power threshold; and (iii) indicating an occurrence of the predetermined signal pulse event when the duration of the received signal pulse is between first and second predetermined duration thresholds of the predefined signal. The predefined signal pulse event can be a radar signal pulse, for example. Embodiments of the present invention can advantageously provide a reliable and simplified approach for radar signal detection suitable for wireless network devices.
摘要翻译：公开了用于无线通信的鲁棒雷达信号检测的方法，算法，架构，电路和/或系统。在一个实施例中，在无线网络设备中检测预定信号脉冲事件的方法可以包括以下步骤：（i）将接收到的信号脉冲的功率与预定信号的预定功率阈值进行比较; （ii）当接收信号脉冲的功率大于预定功率阈值时确定接收信号脉冲的持续时间; 以及（iii）当所述接收信号脉冲的持续时间在所述预定信号的第一和第二预定持续时间阈值之间时，指示所述预定信号脉冲事件的发生。例如，预定信号脉冲事件可以是雷达信号脉冲。本发明的实施例可以有利地提供适用于无线网络设备的雷达信号检测的可靠和简化的方法。

5. 发明申请

US20050278470A1 Polling-based apparatus and system guaranteeing quality of service 有权
标题翻译：基于投票的设备和系统保证服务质量
公开(公告)号：US20050278470A1
公开(公告)日：2005-12-15
申请号：US10864200
申请日：2004-06-09
申请人： Chu-Ming Lin , Shih-Chung Yin
发明人： Chu-Ming Lin , Shih-Chung Yin
IPC分类号： G06F13/36 , G06F13/38 , G06F13/42
CPC分类号： G06F13/385 , G06F13/426
摘要： A polling-based communication apparatus and system. The apparatus of the invention, connected to a host computer through a peripheral bus, comprises an arbiter and multiple addressable entities. Each addressable entity corresponds to one of queues maintained in the host computer. The arbiter can determine which queue is to be served next in accordance with a quality of serve policy. The host computer polls each addressable entity by issuing a query packet. Depending on the queue chosen to be served next, the arbiter grants the corresponding addressable entity access to the peripheral bus, causing this granted addressable entity to respond to the host computer's polling with an acknowledgement packet. Thus the host computer initiates transactions to transfer data packets from the chosen queue through the peripheral bus to the corresponding addressable entity.
摘要翻译：一种基于轮询的通信设备和系统。通过外围总线连接到主计算机的本发明的装置包括仲裁器和多个可寻址实体。每个可寻址实体对应于主计算机中维护的一个队列。仲裁者可以根据服务质量确定下一个服务队列。主机通过发出查询数据包来轮询每个可寻址实体。根据选择接下来服务的队列，仲裁器授予相应的可寻址实体对外围总线的访问，使该授权的可寻址实体用确认分组对主计算机的轮询作出响应。因此，主计算机启动事务以将数据分组从所选择的队列通过外围总线传送到相应的可寻址实体。

6. 发明申请

US20070115960A1 De-interleaver for data decoding 审中-公开
标题翻译：去交织器用于数据解码
公开(公告)号：US20070115960A1
公开(公告)日：2007-05-24
申请号：US11267752
申请日：2005-11-04
申请人： Shih-Chung Yin
发明人： Shih-Chung Yin
IPC分类号： H04L12/56
CPC分类号： H04L1/0045 , H04L1/0059 , H04L1/0071 , H04L27/2601
摘要： A de-interleaver for data decoding. Two memory banks are configured to store data in column order and output the data in row order. A de-interleaving encoder receives a stream of interleaved data values, generates an input address for both the two memory banks contingent upon a modulation mode and based on a count value, and sequentially writes the interleaved data values to either of the memory banks according to the input address. Additionally, a de-interleaving decoder generates respective output addresses for the two memory banks based on a second count value and contingent upon the modulation mode, and a dummy insertion indicator. The de-interleaving decoder reads the interleaved data values from the two memory banks according to the respective output address, and extracts decision metrics from the read data according to relevant output indicators.
摘要翻译：用于数据解码的解交织器。两个存储体被配置为以列顺序存储数据，并以行顺序输出数据。解交织编码器接收交织数据流的流，根据调制模式生成两个存储体两者的输入地址，并根据计数值，依次按顺序将交错数据值写入存储体输入地址。此外，解交织解码器基于第二计数值并且根据调制模式生成两个存储体的相应输出地址，以及虚拟插入指示符。解交织解码器根据相应的输出地址从两个存储体读取交织的数据值，并根据相关的输出指示符从读取的数据中提取决策度量。

7. 发明申请

US20070076683A1 Low power module for a station of a wireless communication system and related method 审中-公开
标题翻译：用于无线通信系统站的低功率模块及相关方法
公开(公告)号：US20070076683A1
公开(公告)日：2007-04-05
申请号：US11241743
申请日：2005-09-30
申请人： Ching Chung , Shih-Chung Yin
发明人： Ching Chung , Shih-Chung Yin
IPC分类号： H04J3/06
CPC分类号： H04W52/0216 , H04W52/0293 , Y02D70/142
摘要： The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX) The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
摘要翻译：本发明涉及一种低功率模块，特别涉及应用于无线通信系统的站中的低功率模块。低功率模块包括第一MAC模块，第二MAC模块，低功率开关寄存器，控制寄存器单元，慢时钟发生器和多路复用器（MUX）。第一和第二MAC模块以正常的方式发送和接收分组操作模式和省电模式。低功率开关寄存器将当前模式切换到另一种模式。控制寄存器单元在低功率开关寄存器的控制下控制RF / BB模块和时钟发生器。在省电模式下，慢时钟发生器为第二个MAC模块生成一个缓慢的工作时钟。 MUX根据控制寄存器单元周期性地选择正常操作或慢操作时钟作为第二MAC模块的时钟。

8. 发明授权

US07020155B2 Collision detection method and apparatus for multiple access communication system 有权
公开(公告)号：US07020155B2
公开(公告)日：2006-03-28
申请号：US09964478
申请日：2001-09-28
申请人： Ching-Kae Tzou , Shih-Chung Yin , Shuenn-Ren Liu , Min-Chieh Chen
发明人： Ching-Kae Tzou , Shih-Chung Yin , Shuenn-Ren Liu , Min-Chieh Chen
IPC分类号： H04L12/413
CPC分类号： H04L12/413 , H04L2012/40247
摘要： A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

9. 发明授权

US08724531B2 Low power module for a station of a wireless communication system and related method 有权
标题翻译：用于无线通信系统站的低功率模块及相关方法
公开(公告)号：US08724531B2
公开(公告)日：2014-05-13
申请号：US12820403
申请日：2010-06-22
申请人： Ching An Chung , Shih-Chung Yin
发明人： Ching An Chung , Shih-Chung Yin
IPC分类号： G08C17/00
CPC分类号： H04W52/0216 , H04W52/0293 , Y02D70/142
摘要： The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
摘要翻译：本发明涉及一种低功率模块，特别涉及应用于无线通信系统的站中的低功率模块。低功率模块包括第一MAC模块，第二MAC模块，低功率开关寄存器，控制寄存器单元，慢时钟发生器和多路复用器（MUX）。第一和第二MAC模块分别以正常操作模式和省电模式发送和接收分组。低功率开关寄存器将当前模式切换到另一种模式。控制寄存器单元在低功率开关寄存器的控制下控制RF / BB模块和时钟发生器。在省电模式下，慢时钟发生器为第二个MAC模块生成一个缓慢的工作时钟。 MUX根据控制寄存器单元周期性地选择正常操作或慢操作时钟作为第二MAC模块的时钟。

10. 发明授权

US07697533B2 Communication device and method 有权
标题翻译：通讯装置及方法
公开(公告)号：US07697533B2
公开(公告)日：2010-04-13
申请号：US11751076
申请日：2007-05-21
申请人： Shang-Ho Tsai , Shih-Chung Yin , Po-Yuen Cheng , Chung-Yen Huang
发明人： Shang-Ho Tsai , Shih-Chung Yin , Po-Yuen Cheng , Chung-Yen Huang
IPC分类号： H04L12/56
CPC分类号： H04L1/0054 , H04W28/18
摘要： A communication device and a method of processing input data. The communication device, processing input data constituting at least one of data packet comprises a detection unit, an Automatic Gain Controller (AGC), a signal processor, a demodulator, a pre-detection module, and a Baseband module. The detection unit receives the input data to perform the packet detection. The Automatic Gain Controller, coupled to the detection unit, generates an adjusted data and a gain control parameter once packet is detected. The signal processor, coupled to the AGC, performs the data signal processing includes at least one of analog to digital transformation processing, radio frequency processing and baseband processing, and detects at least one of the desired signal, noise and interference. The demodulator, coupled to the signal processor, demodulates the processed data into a processed data according to at least one processing function of noise reduction, interference reduction, and signal compensation. The pre-detection module, coupled to the demodulator, determines whether a potential error has occurred in the demodulated input data by a pre-detection method prior completing retrieval of the data packet for performing a packet-based error check sequence, and performs a selection to decide whether the components need to be terminated and which of the components need to be terminated if there is a potential error occurred on the demodulated input data. The Baseband module, coupled to the demodulator, performs a packet-based error check on the data packet upon completing retrieval of the data packet if there is no potential error occurred on the demodulated input data.
摘要翻译：通信设备和处理输入数据的方法。通信设备处理构成数据分组中的至少一个的输入数据包括检测单元，自动增益控制器（AGC），信号处理器，解调器，预检测模块和基带模块。检测单元接收输入数据以执行分组检测。一旦检测到包，耦合到检测单元的自动增益控制器产生经调整的数据和增益控制参数。耦合到AGC的信号处理器执行数据信号处理，包括模数转换处理，射频处理和基带处理中的至少一个，并且检测期望的信号，噪声和干扰中的至少一个。耦合到信号处理器的解调器根据噪声降低，干扰减少和信号补偿的至少一个处理功能将经处理的数据解调为处理数据。耦合到解调器的预检测模块在完成用于执行基于分组的错误检查序列的数据分组的检索之前通过预检测方法确定解调输入数据中是否发生了潜在错误，并且执行选择如果在解调的输入数据上发生潜在错误，则决定是否需要终止组件以及哪些组件需要终止。如果在解调输入数据上没有发生潜在错误，则耦合到解调器的基带模块在完成数据分组的检索时对数据分组执行基于分组的错误检查。

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