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1. 发明授权

US07710774B2 NAND type multi-bit charge storage memory array and methods for operating and fabricating the same 有权
标题翻译： NAND型多位电荷存储器阵列及其操作和制造方法
公开(公告)号：US07710774B2
公开(公告)日：2010-05-04
申请号：US11285919
申请日：2005-11-23
申请人： Yin Jen Chen , Chun Lein Su , Ming Shiang Chin , Chih Chieh Yeh , Tzung Ting Han
发明人： Yin Jen Chen , Chun Lein Su , Ming Shiang Chin , Chih Chieh Yeh , Tzung Ting Han
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11568
摘要： A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.
摘要翻译： NAND型多位电荷存储存储器阵列包括第一和第二存储器串，每个存储器串包括一个或多个电荷存储存储单元和两个选择晶体管。电荷存储存储单元串联连接以形成存储单元串。两个选择晶体管分别串联连接到存储单元串的两端。 NAND型多位电荷存储存储器阵列还包括共享位线和第一位线和第二位线。共享位线与第一和第二存储器串的第一端连接。第一和第二位线分别连接到第一和第二存储器串的第二端。每个存储器串的第一选择晶体管和第二选择晶体管分别由第一和第二选择晶体管控制线控制。

2. 发明授权

US06841446B2 Fabrication method for a flash memory device 有权
标题翻译：闪存器件的制造方法
公开(公告)号：US06841446B2
公开(公告)日：2005-01-11
申请号：US10338999
申请日：2003-01-08
申请人： Chun-Lein Su , Tzung-Ting Han
发明人： Chun-Lein Su , Tzung-Ting Han
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： In a fabrication method of a flash memory device, a first oxide layer is formed on the substrate in the memory cell region and in the peripheral circuit region. A first conductive layer is formed and defined to form a plurality of floating gates in the memory cell region. A second oxide layer and a silicon nitride layer are sequentially formed in the memory cell region and in the peripheral circuit region. The first conductive layer, the second oxide layer and the silicon nitride layer in the peripheral circuit region are removed. A doped region is formed in the peripheral circuit region. A third oxide layer is formed in the memory cell region and in the peripheral circuit region by wet rapid thermal oxidation. Thereafter, a second conductive layer is deposited to form concurrently a control gate in the memory cell region and a gate in the peripheral circuit region.
摘要翻译：在闪速存储器件的制造方法中，在存储单元区域和外围电路区域中的衬底上形成第一氧化物层。形成并限定第一导电层以在存储单元区域中形成多个浮动栅极。在存储单元区域和周边电路区域中依次形成第二氧化物层和氮化硅层。外围电路区域中的第一导电层，第二氧化物层和氮化硅层被去除。在外围电路区域中形成掺杂区域。通过湿快速热氧化在存储单元区域和外围电路区域中形成第三氧化物层。此后，沉积第二导电层以同时形成存储单元区域中的控制栅极和外围电路区域中的栅极。

3. 发明授权

US06624023B1 Method for improving the performance of flash memory 有权
标题翻译：提高闪存性能的方法
公开(公告)号：US06624023B1
公开(公告)日：2003-09-23
申请号：US10152585
申请日：2002-05-23
申请人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
发明人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/954
摘要： The method for improving the performance of flash memory. A substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate, structure are formed on the tunnel oxide layer. The gate structure including a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO layer on the floating gate, a second polysilicon layer as a control gate on the interpoly dielectric layer. Moreover, the poly stringer is exit between the gates, wherein the poly stringer is unmovied after etched. Next, the oxygen free radical process cell oxidation is processed. The results ONO encroachment is very slightly then improvement of 6% GCR with pre-mixing gas process cell oxidation can increase operation speed by more than 5 times and eliminated poly stringer.
摘要翻译：提高闪存性能的方法。证明了底物。在衬底上形成隧道氧化物层。在隧道氧化层上形成两个门，结构。栅极结构包括作为浮置栅极的第一多晶硅层，浮置栅极上的诸如ONO层的多晶硅间介质层，作为在多晶硅间介电层上的控制栅极的第二多晶硅层。此外，多晶硅在栅极之间离开，其中多晶硅在蚀刻后不被剥离。接下来，处理氧自由基过程电池氧化。结果ONO侵蚀非常轻微，然后改进6％GCR，预混合气体处理池氧化可以将操作速度提高5倍以上，消除多边形。

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