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1. 发明授权

US08244880B2 Connection management method, system, and program product 失效
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US08244880B2
公开(公告)日：2012-08-14
申请号：US12191336
申请日：2008-08-14
申请人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
发明人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F12/0875 , G06F12/122 , H04L49/90 , H04L67/14 , H04L69/28
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

2. 发明授权

US08036243B2 Single chip protocol converter 失效
标题翻译：单芯片协议转换器
公开(公告)号：US08036243B2
公开(公告)日：2011-10-11
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

3. 发明申请

US20080192749A1 METHOD AND SYSTEM OF EFFICIENT PACKET REORDERING 失效
标题翻译：高效包装的方法与系统
公开(公告)号：US20080192749A1
公开(公告)日：2008-08-14
申请号：US12105968
申请日：2008-04-18
申请人： Christos J. GEORGIOU , Valentina Salapura
发明人： Christos J. GEORGIOU , Valentina Salapura
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

4. 发明授权

US5402416A Method and system for buffer occupancy reduction in packet switch network 失效
标题翻译：分组交换网络缓存占用率减少的方法和系统
公开(公告)号：US5402416A
公开(公告)日：1995-03-28
申请号：US177873
申请日：1994-01-05
申请人： Randall A. Cieslak , Christos J. Georgiou , Chung-Sheng Li
发明人： Randall A. Cieslak , Christos J. Georgiou , Chung-Sheng Li
IPC分类号： H04M7/00 , H04L12/56 , H04L12/64 , H04Q11/04
CPC分类号： H04L47/10 , H04L12/64
摘要： A packet switch system having a buffer occupancy reduction mechanism for controlling data flow through switched nodes of the system to avoid congestion and reduce required buffer storage at the nodes. For an isochronous connection, buffers are initially allocated at each switching node connection to ensure listless transmission of packets. A buffer occupancy trace for the connection is recorded and the delay time of an isochronous packet at a particular switch port is returned to a preceding switch port. The preceding switch port employs the feedback message to delay subsequent packets through the connection to reduce the queuing time at the particular switch port. Once the isochronous connection has stabilized, buffer reallocation is performed wherein a scheduler at each switch node along the connection attempts to combine buffer allocations for different isochronous connections. This occurs provided the corresponding buffer occupancy traces of the isochronous connections do not overlap. Buffer occupancy reduction is therefore accomplished through the delaying of isochronous packets propagated through the connections of the packet switch system and the reallocating of buffers initially assigned to two or more isochronous connections.
摘要翻译：一种分组交换系统，具有缓冲占用减少机制，用于控制通过系统的交换节点的数据流，以避免拥塞并减少节点处所需的缓冲存储。对于等时连接，最初在每个交换节点连接处分配缓冲区，以确保数据包的无干扰传输。记录连接的缓冲占用轨迹，并将特定交换机端口上的等时数据包的延迟时间返回到前一个交换机端口。上述交换机端口采用反馈消息来延迟通过连接的后续分组，以减少特定交换机端口的排队时间。一旦同步连接已经稳定，则执行缓冲器重新分配，其中沿着连接的每个交换节点处的调度器尝试组合用于不同等时连接的缓冲器分配。如果同步连接的相应缓冲区占用轨迹不重叠，则会发生这种情况。因此，通过延迟通过分组交换系统的连接传播的同步分组和最初分配给两个或多个同步连接的缓冲区的重新分配来实现缓冲器占用减少。

5. 发明授权

US5235592A Dynamic switch protocols on a shared medium network 失效
标题翻译：一个共享媒体网络的动态切换协议
公开(公告)号：US5235592A
公开(公告)日：1993-08-10
申请号：US744153
申请日：1991-08-13
申请人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
发明人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
IPC分类号： H04L12/417 , H04L29/06
CPC分类号： H04L29/06 , H04L12/417
摘要： Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume. The use of circuit switched protocols within a token bus protocol allows more general transmission sequences and improves the utilization of token bus bandwidth.

6. 发明授权

US4929940A Collision crossbar switch 失效
标题翻译：碰撞横梁开关
公开(公告)号：US4929940A
公开(公告)日：1990-05-29
申请号：US275164
申请日：1988-11-18
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： H04Q3/52 , H04Q11/04
CPC分类号： H04L49/101 , H04L49/252 , H04Q11/04
摘要： A high speed collision N.times.M tri-state crossbar switch having M collision busses uses contention detection at the destination. In the event of a collision of messages, remedial action can be taken such as rerouting colliding messages over an alternate path provided by a second interconnection network with contention resolution capability. Collision detection codes are transmitted prior to the transmission of messages to each input port. The tri-state output buses are monitored for the collison detection codes to detect an error. In order to prevent damage to driver transistors connected to the tri-state buses when a contention occurs, current limiting is provided to limit the current through the driver transistors to a predetermined level.

7. 发明授权

US4635250A Full-duplex one-sided cross-point switch 失效
标题翻译：全双工单向交叉点开关
公开(公告)号：US4635250A
公开(公告)日：1987-01-06
申请号：US599874
申请日：1984-04-13
申请人： Christos J. Georgiou
发明人： Christos J. Georgiou
IPC分类号： H03K17/00 , H04Q3/52 , H04Q3/00
CPC分类号： H04Q3/521
摘要： A full-duplex one-sided switching chip comprising externally connected lines as input/output pairs and pairs of bi-directional interconnection lines. Duplex cross-points selectively connect input/output line pairs to the interconnection line pairs. The interconnection lines can be coupled to interconnection lines on other chips for multichip switching arrays.
摘要翻译：一种全双工单向切换芯片，包括外部连接的线路作为输入/输出对和双向互连线对。双工交叉点选择性地将输入/输出线对连接到互连线对。互连线可以耦合到用于多芯片开关阵列的其它芯片上的互连线。

8. 发明授权

US4630045A Controller for a cross-point switching matrix 失效
标题翻译：用于交叉点开关矩阵的控制器
公开(公告)号：US4630045A
公开(公告)日：1986-12-16
申请号：US544653
申请日：1983-10-24
申请人： Christos J. Georgiou
发明人： Christos J. Georgiou
IPC分类号： H04Q3/545 , H04Q3/52 , H04Q9/00
CPC分类号： H04Q3/521
摘要： A controller for controlling a one-sided switching matrix comprising a plurality of circuit elements under the control of logic circuitry. The controller interprets a request for connection or disconnection, determines if it is possible, selects a path through the matrix and sends control signals to the matrix. The circuit elements are arranged in a parallel/pipeline architecture with multiple circuit elements simultaneously operating on a request. The controller can fetch a second request while executing a first request. The result of a request is to connect or disconnect interconnection paths on the switching matrix.
摘要翻译：一种用于在逻辑电路的控制下控制包括多个电路元件的单面开关矩阵的控制器。控制器解释连接或断开请求，确定是否可能，选择通过矩阵的路径，并向矩阵发送控制信号。电路元件被布置成并行/流水线架构，其中多个电路元件同时根据请求进行操作。执行第一个请求时，控制器可以获取第二个请求。请求的结果是连接或断开交换矩阵上的互连路径。

9. 发明授权

US07574524B2 Method and system for on-demand allocation of a dynamic network of services 失效
标题翻译：动态服务网络按需分配的方法和系统
公开(公告)号：US07574524B2
公开(公告)日：2009-08-11
申请号：US10674962
申请日：2003-09-30
申请人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
发明人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L67/1008 , H04L67/1002 , H04L67/1029
摘要： A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.
摘要翻译：一种用于在第一和第二服务提供商之间提供实时动态切换的系统和方法，每个服务提供商能够通过通信网络为用户提供服务。该方法包括以下步骤：建立用于决定何时切换第一服务提供商和第二服务提供商之间的服务提供的切换标准; 维护与用户对由第一服务提供商提供的服务的使用相关联的状态信息; 基于切换标准的满足，在通信网络上提供的第一和第二服务之间切换; 并且将维护的任何状态信息迁移到切换到第二服务的时间。优选地，动态切换以对用户基本透明的方式发生。

10. 发明授权

US5550860A Digital phase alignment and integrated multichannel transceiver employing same 失效
标题翻译：采用数字相位校准和集成多通道收发器
公开(公告)号：US5550860A
公开(公告)日：1996-08-27
申请号：US420102
申请日：1995-04-11
申请人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
发明人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
IPC分类号： H03M9/00 , H04L7/033 , H04L25/34
CPC分类号： H04L7/0338 , H03M9/00 , H04L7/005
摘要： A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.
摘要翻译：提供信号平滑和滤波功能以及滑动周期补偿的同步器和相位对准方法，并且允许多通道数字相位对准，总线偏移校正，在单个半导体芯片内集成多个收发器等。延迟线产生多个的输入信号的延迟输入副本。时钟相位调节器从参考时钟信号产生采样时钟信号。采样时钟信号可以被相位调整以偏离输入信号。经过一定的平滑和滤波功能后，选择逻辑检测采样时钟信号和输入副本之间的相位关系，并识别紧密同步的信号进行输出。使用该识别的复制信号，打滑周期补偿和重新定时逻辑输出与参考时钟信号同步的补偿数据输出信号。此外，提出了使用相位对准技术制造的集成多收发器。

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