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1. 发明授权

US5801720A Data transfer from a graphics subsystem to system memory 失效
标题翻译：从图形子系统到系统内存的数据传输
公开(公告)号：US5801720A
公开(公告)日：1998-09-01
申请号：US604008
申请日：1996-02-20
申请人： Forrest E. Norrod , Willard S. Briggs , Christopher G. Wilcox , Brian D. Falardeau , Sameer Y. Nanavati
发明人： Forrest E. Norrod , Willard S. Briggs , Christopher G. Wilcox , Brian D. Falardeau , Sameer Y. Nanavati
IPC分类号： G06F3/14 , G09G5/393 , G06F13/00
CPC分类号： G09G5/393 , G06F3/14 , G09G2360/125
摘要： A processing system includes a graphics subsystem that directly renders raster data to system memory and moves bitmaps between locations within system memory with the graphics subsystem providing the data and a processor providing the virtual-to-physical addresses with privilege and protection check mechanisms.
摘要翻译：处理系统包括图形子系统，其直接将光栅数据呈现给系统存储器并且利用提供数据的图形子系统和处理器为虚拟到物理地址提供特权和保护检查机制来移动系统存储器内的位置之间的位图。

2. 发明授权

US06598136B1 Data transfer with highly granular cacheability control between memory and a scratchpad area 失效
标题翻译：数据传输与存储器和暂存区域之间的高度细粒度的缓存控制
公开(公告)号：US06598136B1
公开(公告)日：2003-07-22
申请号：US08950513
申请日：1997-10-22
申请人： Forrest E. Norrod , Christopher G. Wilcox , Brian D. Falardeau , Willard S. Briggs
发明人： Forrest E. Norrod , Christopher G. Wilcox , Brian D. Falardeau , Willard S. Briggs
IPC分类号： G06F1300
CPC分类号： G06F12/0888 , G06F12/084 , G06F2212/6012
摘要： A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.
摘要翻译：具有CPU核心和高速缓冲存储器的处理系统在第一存储器块和第二存储器块之间传送数据，其优选地作为不可缓存的暂存区域从高速缓存区分离出来，并且在没有污染的情况下执行具有保护和特权检查的地址计算缓存。响应于执行预定指令，CPU内核向高速缓存指示信号，以防止在从系统到暂存器存储器的传输期间缓存数据，从而减少总线周转的数量，同时保持字节粒度可寻址性。

3. 发明授权

US5347634A System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers 失效
标题翻译：通过使用处理器特权工作缓冲区指针，从用户控制进程直接执行用户DMA指令的系统和方法
公开(公告)号：US5347634A
公开(公告)日：1994-09-13
申请号：US494008
申请日：1990-03-15
申请人： Russ W. Herrell , Curtis R. McAllister , Dong Y. Kuo , Christopher G. Wilcox
发明人： Russ W. Herrell , Curtis R. McAllister , Dong Y. Kuo , Christopher G. Wilcox
IPC分类号： G06F13/00 , G06F13/28 , G06F13/38
CPC分类号： G06F13/28
摘要： The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process.
摘要翻译：本发明涉及一种从主机系统解释用户命令的智能直接存储器访问（DMA）控制器，为每个用户进程建立工作缓冲区，并且以用户的请求从工作缓冲区中检索数据块，而不是在内核软件的请求。这通过为锁定到物理内存中的每个用户进程建立工作缓冲区来实现。控制用户进程将填充一个工作缓冲区，获取设备信号量，在锁定的缓冲区上启动物理DMA，然后开始填充另一个缓冲区。通过允许用户通过对应于每个用户进程的每个工作缓冲区的工作缓冲区指针寄存器的工作缓冲区指针，通过允许用户访问用于DMA的工作缓冲区而不知道其在存储器中的物理位置来维持存储器完整性。这些工作缓冲区指针寄存器是特权的，并由主机处理器为每个新的控制用户进程更新。

4. 发明授权

US5764999A Enhanced system management mode with nesting 失效
标题翻译：增强的系统管理模式与嵌套
公开(公告)号：US5764999A
公开(公告)日：1998-06-09
申请号：US541359
申请日：1995-10-10
申请人： Christopher G. Wilcox , Joseph F. Baldwin , Xiaoli Y. Mendyke
发明人： Christopher G. Wilcox , Joseph F. Baldwin , Xiaoli Y. Mendyke
IPC分类号： G06F13/10 , G06F9/455 , G06F9/46 , G06F9/48 , G06F12/02 , G06F11/00
CPC分类号： G06F9/4812 , G06F9/45533 , G06F12/0284
摘要： An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a Virtual System Architecture (VSA) in which peripheral hardware, such as for graphics and/or audio functions, is virtualized (simulated by SMI routines). Reentrant VSA/SMM software (handler) includes VSA/SMI routines invoked either by (a) SMI interrupts, such as from non-virtualized peripheral hardware such as audio FIFO buffers, or (b) SMI traps, such as from accesses to memory mapped or I/O space allocated to a virtualized peripheral function. SMI nesting permits a currently active VSA/SMI routine to be preempted by another (higher priority) SMI event. The SMM memory region includes an SMI header segment and a VSA/SMM software segment--the SMI header segment is organized as a quasi-stack into which nested SMI headers are saved. The VSA/SMM software manages an SMHR register that points to the location for storing the SMI header for a currently active VSA/SMI routine if it is preempted by an SMI event. To improve performance, the entire SMM region is mapped into cacheable system memory. Features that support virtualization include: (a) SMI nesting, (b) SMI trapping for memory (as well as I/O) accesses, (c) caching both VSA/SMI headers and VSA/SMM software, and (d) configuring the SMM region for storing multiple SMI headers at programmable locations.
摘要翻译：增强的系统管理模式（SMM）包括用于处理SMI事件的SMI（系统管理中断）例程的嵌套。增强的SMM在计算机系统中实现以支持虚拟系统架构（VSA），其中诸如用于图形和/或音频功能的外围硬件被虚拟化（由SMI程序模拟）。可重入VSA / SMM软件（处理程序）包括通过（a）SMI中断（例如来自诸如音频FIFO缓冲器的非虚拟化外围硬件）或（b）SMI陷阱（诸如从存储器映射的访问）调用的VSA / SMI例程或分配给虚拟化外设功能的I / O空间。 SMI嵌套允许当前活动的VSA / SMI例程被另一个（较高优先级）的SMI事件抢占。 SMM存储器区域包括SMI标题段和VSA / SMM软件段 - SMI标题段被组织成其中保存嵌套SMI标题的准堆栈。 VSA / SMM软件管理一个SMHR寄存器，如果它被SMI事件抢占，则SMHR寄存器指向用于存储当前活动的VSA / SMI例程的SMI头的位置。为了提高性能，整个SMM区域被映射到可缓存的系统内存中。支持虚拟化的特性包括：（a）SMI嵌套，（b）存储器（以及I / O）访问的SMI陷阱，（c）缓存VSA / SMI头和VSA / SMM软件，以及（d）配置 SMM区域，用于在可编程位置存储多个SMI头。

5. 发明授权

US5416893A Method for displaying edging or decaling of an object in a graphics display 失效
标题翻译：用于在图形显示器中显示对象的边缘或贴花的方法
公开(公告)号：US5416893A
公开(公告)日：1995-05-16
申请号：US143686
申请日：1993-10-26
申请人： Russ Herrell , Joe Baldwin , Christopher G. Wilcox
发明人： Russ Herrell , Joe Baldwin , Christopher G. Wilcox
IPC分类号： G06T11/20 , G06T15/40 , G06T15/10
CPC分类号： G06T15/405
摘要： A system for implementing polygon edging of objects in a graphics display. In a first pass, the system renders the polygon fill with z-buffer comparison and replace enabled, however, for each pixel written to the display frame buffer and z-buffer, an edging plane bit for the pixel is set. A second pass renders the polygon edges with z-buffer comparison and z-buffer replace enabled and uses the edging plane bit as a virgin bit. A third pass re-renders the polygon fill, but only resets the edging plane bit for each pixel. The system may also use a virgin bit available in the z-buffer as the edging plane bit.
摘要翻译：用于在图形显示器中实现对象的多边形边缘的系统。在第一次通过中，系统通过z缓冲区比较并使能多边形填充，然而，对于写入显示帧缓冲区和z缓冲区的每个像素，设置像素的边缘平面位。第二遍通过z-缓冲区比较和Z缓冲区替换启用多边形边缘，并使用边缘平面位作为处女位。第三遍重新渲染多边形填充，但仅复位每个像素的边缘平面位。该系统还可以使用z缓冲器中可用的处女位作为边缘平面位。

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