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1. 发明授权

US07208785B2 Self-aligned Schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods 失效
标题翻译：自对准肖特基势垒夹紧平面DMOS晶体管结构及其制造方法
公开(公告)号：US07208785B2
公开(公告)日：2007-04-24
申请号：US11014837
申请日：2004-12-20
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L29/80
CPC分类号： H01L29/7806 , H01L27/0727 , H01L29/4933 , H01L29/66719
摘要： The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N− epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p− diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.
摘要翻译：自对准肖特基势垒夹紧平面DMOS晶体管结构包括由平面栅极区域包围的自对准源极区域。自对准源极区包括在轻掺杂的N +外延半导体层中形成的中等掺杂的p基扩散环，重掺杂的N + 扩散环形成在中等掺杂的p基扩散环内，并且与作为扩散保护环的中等掺杂的p基扩散环的肖特基势垒接触形成在自对准的p型扩散环的中间半导体表面部分中源区。平面栅极区域包括具有或不具有金属硅化物层的被硅化的图案化重掺杂多晶硅栅极层。自对准源极区还包括在中等掺杂的p基扩散环的中间部分下方形成的轻掺杂的pO - 扩散区。

2. 发明申请

US20060184911A1 Labeling method and software utilizing the same, and PCB and electronic device utilizing the same 审中-公开
标题翻译：使用该标签的方法和软件，以及使用其的PCB和电子设备
公开(公告)号：US20060184911A1
公开(公告)日：2006-08-17
申请号：US11352995
申请日：2006-02-14
申请人： Shu-Chih Chen , Chun-Chi Hsu , Ching-Yuan Wu
发明人： Shu-Chih Chen , Chun-Chi Hsu , Ching-Yuan Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H05K1/0218 , H05K1/0298 , H05K2201/0715 , H05K2201/0723 , H05K2201/09236 , H05K2201/09781 , H05K2201/09972
摘要： A labeling method for a printed circuit board comprising a first layout face and a second layout face opposite to the first layout face. The labeling method comprises defining a track region in the first layout face, defining a first mapping region mapped by the track region on the second layout face; and defining a first corresponding region on the second layout face completely enclosing the first mapping region.
摘要翻译：一种用于印刷电路板的标记方法，包括与第一布局面相对的第一布局面和第二布局面。所述标记方法包括：在所述第一布局面中定义轨道区域，限定由所述第二布局面上的所述轨道区域映射的第一映射区域; 以及在所述第二布局面上定义完全包围所述第一映射区域的第一对应区域。

3. 发明申请

US20060131686A1 LOCOS-based junction-pinched schottky rectifier and its manufacturing methods 审中-公开
标题翻译：基于LOCOS的接合肖特基整流器及其制造方法
公开(公告)号：US20060131686A1
公开(公告)日：2006-06-22
申请号：US11014838
申请日：2004-12-20
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07 , H01L31/108
CPC分类号： H01L27/0814 , H01L29/861 , H01L29/872
摘要： The LOCOS-based junction-pinched Schottky rectifier comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a raised diffusion grid or a plurality of raised diffusion rings or stripes surrounded by the raised diffusion guard ring, a plurality of recessed semiconductor surfaces formed on a lightly-doped epitaxial semiconductor layer surrounded by the raised diffusion guard ring and the raised diffusion grid or by the raised diffusion guard ring and the plurality of raised diffusion rings or stripes, and a metal silicide layer or a metal layer being at least formed over a portion of the raised diffusion guard ring, the plurality of recessed semiconductor surfaces and the raised diffusion grid or the plurality of raised diffusion rings or stripes. A plurality of compensated diffusion layers can be formed in surface portions of the lightly-doped epitaxial semiconductor layer under the plurality of recessed semiconductor surfaces.
摘要翻译：基于LOCOS的接合肖特基整流器包括由外部LOCOS场氧化物层，升高的扩散栅格或由升高的扩散保护环包围的多个凸起扩散环或条包围的隆起的扩散保护环，多个凹陷半导体由被升高的扩散保护环和升高的扩散栅格包围的轻掺杂的外延半导体层上形成的表面或由升高的扩散保护环和多个凸起的扩散环或条形成的金属硅化物层或金属层最小形成在升高的扩散保护环的一部分上，多个凹入的半导体表面和升高的扩散栅格或多个凸起的扩散环或条纹。可以在多个凹入半导体表面下的轻掺杂外延半导体层的表面部分中形成多个补偿扩散层。

4. 发明申请

US20060131646A1 Scalable planar DMOS transistor structure and its fabricating methods 失效
标题翻译：可扩展的平面DMOS晶体管结构及其制造方法
公开(公告)号：US20060131646A1
公开(公告)日：2006-06-22
申请号：US11014836
申请日：2004-12-20
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/66719 , H01L21/266 , H01L29/456 , H01L29/4933 , H01L29/66333
摘要： The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n− epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p+ contact diffusion region and the n+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.
摘要翻译：本发明的可扩展平面DMOS晶体管结构包括由平面栅极区域包围的可缩放的源极区域。可扩展的源区包括通过环形注入窗口形成在外延半导体层中的p基扩散区，在... ...形成的源极扩散环通过环形注入窗口的p型扩散区域的表面部分，通过自对准注入窗口形成在中间半导体表面部分中的接触扩散区域，以及由侧壁电介质间隔物围绕的p + +接触扩散区和n + SUP源极扩散环上形成的自对准源极接触窗。平面栅极区域包括图案化的重掺杂多晶硅栅极层，其形成在栅极电介质层上并且在有或没有金属硅化物层的情况下局部封盖。

5. 发明申请

US20060131619A1 Self-aligned schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods 失效
标题翻译：自对准肖特基势垒夹紧平面DMOS晶体管结构及其制造方法
公开(公告)号：US20060131619A1
公开(公告)日：2006-06-22
申请号：US11014837
申请日：2004-12-20
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L29/80 , H01L29/76
CPC分类号： H01L29/7806 , H01L27/0727 , H01L29/4933 , H01L29/66719
摘要： The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N− epitaxial semiconductor layer, a heavily-doped n+ source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p− diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.
摘要翻译：自对准肖特基势垒夹紧平面DMOS晶体管结构包括由平面栅极区域包围的自对准源极区域。自对准源极区包括在轻掺杂的N +外延半导体层中形成的中等掺杂的p基扩散环，重掺杂的N + 扩散环形成在中等掺杂的p基扩散环内，并且与作为扩散保护环的中等掺杂的p基扩散环的肖特基势垒接触形成在自对准的p型扩散环的中间半导体表面部分中源区。平面栅极区域包括具有或不具有金属硅化物层的被硅化的图案化重掺杂多晶硅栅极层。自对准源极区还包括在中等掺杂的p基扩散环的中间部分下方形成的轻掺杂的pO - 扩散区。

6. 发明申请

US20060108680A1 Multi-layer printed circuit board wiring layout and method for manufacturing the same 失效
标题翻译：多层印刷电路板布线及其制造方法
公开(公告)号：US20060108680A1
公开(公告)日：2006-05-25
申请号：US11285334
申请日：2005-11-22
申请人： Ching-Yuan Wu , Kuang-Jen Liu , Chun-Chi Hsu
发明人： Ching-Yuan Wu , Kuang-Jen Liu , Chun-Chi Hsu
IPC分类号： H01L23/04 , H05K7/06
CPC分类号： H05K1/115 , H05K3/421 , H05K3/429 , H05K2201/0394 , H05K2201/09509 , H05K2201/09836
摘要： A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.
摘要翻译：多层印刷电路板（PCB）包括第一布线层，第一布线层之上的中间层，中间层上方的第二布线层和形成在中间层和第二布线层中的倾斜孔。该制造方法包括以下步骤：在第一布线层上形成第一布线层并形成第一布线，在第一布线层上形成中间层，在中间层上形成第二布线层，在中间层形成倾斜孔层和第二线层，其中倾斜通孔的方向不与第一和第二线层正交，通过蚀刻方法在第二线层上形成第二布线，并且在通孔中形成电镀层以连接第一布线和第二布线。

7. 发明授权

US06992353B1 Self-aligned source structure of planar DMOS power transistor and its manufacturing methods 失效
标题翻译：平面DMOS功率晶体管的自对准源结构及其制造方法
公开(公告)号：US06992353B1
公开(公告)日：2006-01-31
申请号：US10976886
申请日：2004-11-01
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66719 , H01L29/456
摘要： A self-aligned source structure is disclosed by the present invention, in which a p-body diffusion region is formed in an n− epitaxial silicon layer on an n+ silicon substrate through a patterned window; a p+ diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sidewall dielectric spacer being formed over and on a silicon nitride layer; an n+ source diffusion ring is formed in a surface portion of the p-body diffusion region and on an extended portion of the p+ diffusion region through a second self-aligned implantation window formed between the silicon nitride layer and a masking layer surrounded by the first sidewall dielectric spacer; and a self-aligned source contact window is formed on the n+ source diffusion ring surrounded by a second sidewall dielectric spacer and on the p+ diffusion region surrounded by the n+ source diffusion ring.
摘要翻译：本发明公开了一种自对准源结构，其中在n + +硅衬底上的n +外延硅层中形成p体扩散区通过图案化的窗户; 通过由形成在氮化硅层上面和之上的第一侧壁电介质隔离片围绕的第一自对准注入窗口在p体扩散区域内形成p + +扩散区域; 在p体扩散区的表面部分和p + +扩散区域的延伸部分上通过第二自对准形成n + 在氮化硅层和由第一侧壁电介质隔离物围绕的掩蔽层之间形成的注入窗口; 并且在由第二侧壁电介质隔离物围绕的n + SUP电极扩散环上和在由n'包围的p + +扩散区上形成自对准源极接触窗口， SUP> + 源扩散环。

8. 发明授权

US06750499B2 Self-aligned trench-type dram structure and its contactless dram arrays 失效
标题翻译：自对准沟槽式电镀结构及其非接触式电极阵列
公开(公告)号：US06750499B2
公开(公告)日：2004-06-15
申请号：US10212225
申请日：2002-08-06
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L2976
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.
摘要翻译：通过本发明公开了包括自对准DRAM电容器结构和自对准DRAM晶体管结构的自对准沟槽型DRAM结构，其中自对准DRAM电容器结构包括深沟槽电容器区域和浅沟槽隔离区域由间隔物技术限定，并且自对准DRAM晶体管结构包括由另一间隔物技术限定的可伸缩栅极叠层区域和共漏极区域。自对准沟槽型DRAM结构用于实现两个非接触式DRAM阵列。第一类非接触DRAM阵列包括与平坦化的共漏极导电岛和多个高导电性字线集成的多个金属位线。第二类非接触式DRAM阵列包括与平坦化导电栅极岛和多个公共漏极导电位线集成的多个金属字线。

9. 发明授权

US06746918B2 Methods of fabbricating a stack-gate non-volatile memory device and its contactless memory arrays 失效
标题翻译：堆叠栅极非易失性存储器件及其非接触存储器阵列的制造方法
公开(公告)号：US06746918B2
公开(公告)日：2004-06-08
申请号：US10170453
申请日：2002-06-14
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.
摘要翻译：具有锥形浮栅结构的堆叠栅极非易失性存储器件由本发明公开，其中锥形浮栅结构提供更长的有效通道长度以减轻穿通效应和较大的表面积在锥形浮栅结构和集成的公共源极/漏极导电结构之间进行擦除或编程。本发明的堆叠门非易失性存储器件被实现为三个非接触阵列结构：非接触式NOR型阵列，无连接NAND型阵列和非接触式并行共源/漏极导电位线阵列。非接触式存储器阵列的特征和优点是4F 2的较小的单元尺寸，较小的共源/漏极总线电阻和电容，更高的擦除速度以及较小的位/字线电阻和电容，与现有技术相比。

10. 发明授权

US06734484B2 Vertical transistor DRAM structure and its manufacturing methods 失效
标题翻译：垂直晶体管DRAM结构及其制造方法
公开(公告)号：US06734484B2
公开(公告)日：2004-05-11
申请号：US10227438
申请日：2002-08-26
申请人： Ching-Yuan Wu
发明人： Ching-Yuan Wu
IPC分类号： H01L31116
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L29/945
摘要： A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.
摘要翻译：通过本发明公开了一种垂直晶体管DRAM结构，其中沟槽结构包括具有垂直晶体管的深沟槽区域和形成在深沟槽区域的侧部中的第二类型的浅沟槽隔离区域并且共漏极结构包括在深沟槽区域的另一侧部分中的共漏极扩散区域下方形成不同的注入区域。垂直晶体管DRAM结构用于实现两个非接触式DRAM阵列。第一类非接触DRAM阵列包括多个金属位线。具有平面化的共漏极导电岛和多个高导电性字线。第二类非接触DRAM阵列包括与平坦化共栅导电岛和多个公共漏极导电位线集成的多个金属字线。

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