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1. 发明申请

US20120112330A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120112330A1
公开(公告)日：2012-05-10
申请号：US13195454
申请日：2011-08-01
申请人： Ping-Chia Liao , Chin-Yung Chen , Chun-Chieh Yang
发明人： Ping-Chia Liao , Chin-Yung Chen , Chun-Chieh Yang
IPC分类号： H01L23/495
CPC分类号： H01L23/4985 , H01L21/4842 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as a semiconductor device of chip on film package, is provided. The semiconductor device includes at least an integrated circuit formed on a film base, each integrated circuit includes a chip and a plurality of leads formed interior to a boundary of a predetermined range, each lead is formed with a predetermined distance from the boundary. While the integrated circuit is punched from the film base along the boundary, conductive residue of leads left on the puncher is therefore reduced or avoided.
摘要翻译：提供半导体器件，例如薄膜封装上的芯片的半导体器件。半导体器件至少包括形成在膜基底上的集成电路，每个集成电路包括芯片和形成在预定范围的边界内部的多个引线，每个引线形成与边界预定的距离。虽然集成电路沿着边界从膜基底冲压，因此减少或避免了冲孔机上留下的导线的导电残留物。

2. 发明授权

US07745726B2 Assembly structure 有权
标题翻译：装配结构
公开(公告)号：US07745726B2
公开(公告)日：2010-06-29
申请号：US12125250
申请日：2008-05-22
申请人： Ming-Te Lin , Chin-Yung Chen
发明人： Ming-Te Lin , Chin-Yung Chen
IPC分类号： H02G15/00 , H01R9/00
CPC分类号： H05K3/361 , H05K1/117 , H05K3/323 , H05K2201/09418 , Y10T428/24752 , Y10T428/31504
摘要： An assembly structure is provided. The assembly structure includes a first substrate, a second substrate and a medium layer disposed between the first and second substrates. The medium layer includes a side edge, and the second substrate includes at least one lead wire. When the second substrate is disposed on the medium layer, the lead wire of the second substrate is relatively oblique to the side edge of the medium layer.
摘要翻译：提供组装结构。组装结构包括第一衬底，第二衬底和布置在第一和第二衬底之间的介质层。所述介质层包括侧边缘，并且所述第二基板包括至少一根引线。当第二基板设置在介质层上时，第二基板的引线相对于介质层的侧边缘倾斜。

3. 发明申请

US20100129963A1 INTEGRATED CIRCUIT PACKAGE AND FABRICATING METHOD THEREOF 有权
标题翻译：集成电路封装及其制作方法
公开(公告)号：US20100129963A1
公开(公告)日：2010-05-27
申请号：US12694239
申请日：2010-01-26
申请人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
发明人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
IPC分类号： H01L21/60
CPC分类号： H01L23/3735 , H01L23/3677 , H01L24/48 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.
摘要翻译：本发明公开了一种集成电路封装。集成电路封装包括具有第一表面和与其相对的第二表面的基板以及从第一表面到第二表面穿过基板的第一孔。多个导电线设置在基板的第二表面的一部分上。半导体芯片设置在衬底的第二表面上方，其中在半导体芯片和衬底之间形成腔室。多个接合焊盘设置在半导体芯片的朝向衬底的第二表面的一侧上，其中至少一个接合焊盘电连接到多条导线之一。第一散热层设置在第一孔中并延伸到腔室中。还提供了一种用于制造集成电路封装的方法。

4. 外观设计

USD450972S1 CD rack 失效
标题翻译： CD架
公开(公告)号：USD450972S1
公开(公告)日：2001-11-27
申请号：US29141661
申请日：2001-05-11
申请人： Chin-Yung Chen
设计人： Chin-Yung Chen

5. 发明授权

US07829388B2 Integrated circuit package and fabricating method thereof 有权
标题翻译：集成电路封装及其制造方法
公开(公告)号：US07829388B2
公开(公告)日：2010-11-09
申请号：US12694239
申请日：2010-01-26
申请人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
发明人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
IPC分类号： H01L21/00
CPC分类号： H01L23/3735 , H01L23/3677 , H01L24/48 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.
摘要翻译：本发明公开了一种集成电路封装。集成电路封装包括具有第一表面和与其相对的第二表面的基板以及从第一表面到第二表面穿过基板的第一孔。多个导电线设置在基板的第二表面的一部分上。半导体芯片设置在衬底的第二表面上方，其中在半导体芯片和衬底之间形成腔室。多个接合焊盘设置在半导体芯片的朝向衬底的第二表面的一侧上，其中至少一个接合焊盘电连接到多条导线之一。第一散热层设置在第一孔中并延伸到腔室中。还提供了一种用于制造集成电路封装的方法。

6. 发明授权

US07804169B2 Integrated circuit package and fabricating method thereof 有权
公开(公告)号：US07804169B2
公开(公告)日：2010-09-28
申请号：US12102439
申请日：2008-04-14
申请人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
发明人： Chin-Yung Chen , Chia-Hung Hsu , William Wang , Chung-Cheng Chou
IPC分类号： H01L23/10
CPC分类号： H01L23/3735 , H01L23/3677 , H01L24/48 , H01L2224/16 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention discloses an integrated circuit package. The integrated circuit package comprises a substrate having a first surface and a second surface opposite thereto and a first hole passing through the substrate from the first surface to the second surface. A plurality of conductive lines is disposed on a portion of the second surface of the substrate. A semiconductor chip is disposed above the second surface of the substrate, wherein a chamber is formed between the semiconductor chip and the substrate. A plurality of bonding pads are disposed on a side of the semiconductor chip which is toward the second surface of the substrate, wherein at least one of the bonding pads are electrically connected to one of the plurality of conductive lines. A first heat dissipation layer is disposed in the first hole, and extends into the chamber. A method for fabricating the integrated circuit package is also provided.

7. 发明申请

US20090242281A1 TOUCH SENSING DEVICE AND TOUCH SENSING APPARATUS 有权
标题翻译：触摸感应装置和触摸感应装置
公开(公告)号：US20090242281A1
公开(公告)日：2009-10-01
申请号：US12139833
申请日：2008-06-16
申请人： Chung-Cheng CHOU , William WANG , Chia-Hung HSU , Chin-Yung CHEN
发明人： Chung-Cheng CHOU , William WANG , Chia-Hung HSU , Chin-Yung CHEN
IPC分类号： G06F3/041
CPC分类号： G06F3/041
摘要： The invention discloses a touch sensing device, which includes a containing space, a first substrate layer, a second substrate layer, a driver, and a sensor. The first substrate layer and the second substrate layer define the containing space for containing a fluid. The driver can provide charges to a first conducting layer of the first substrate layer, a second conducting layer of the second substrate layer, and the fluid. The sensor can sense the electric characteristics of the fluid. When a point unit approaches the touch sensing device and influences the charges, the appearance of the fluid could be changed and then the electric characteristics could also be changed.
摘要翻译：本发明公开了一种触摸感测装置，其包括容纳空间，第一基板层，第二基板层，驱动器和传感器。第一衬底层和第二衬底层限定用于容纳流体的容纳空间。驱动器可以向第一衬底层的第一导电层，第二衬底层的第二导电层和流体提供电荷。传感器可感测流体的电气特性。当点单元接近触摸感测装置并影响电荷时，可以改变流体的外观，然后电特性也可以改变。

8. 发明申请

US20070100924A1 Asynchronous signed multiplier and algorithm thereof 审中-公开
标题翻译：异步有符号乘法器及其算法
公开(公告)号：US20070100924A1
公开(公告)日：2007-05-03
申请号：US11264428
申请日：2005-10-31
申请人： Chin-Yung Chen , Kuang-Shyr Wu
发明人： Chin-Yung Chen , Kuang-Shyr Wu
IPC分类号： G06F7/52
CPC分类号： G06F7/5306 , G06F7/74 , G06F2207/3864
摘要： An asynchronous signed multiplier including N pieces of partial product generators (PPGs), an operation module and a leading-zero-bit-detector is provided. The partial product generator generates a plurality of partial product values in response to a multiplier and a multiplicand. The operation module conducts a sum-up operation on the outputs from the (N-1)-th PPG to the first PPG, and the output from the N-th PPG is added in the end. In addition, as the leading-zero-bit-detector detects any leading-zero-bit in the multiplier or the multiplicand, the partial product outputs corresponding to the bit of “0” is directly set to zero.
摘要翻译：提供了包括N个部分乘积生成器（PPG），操作模块和前置零位检测器的异步签名乘数。部分积发生器响应于乘法器和被乘数产生多个部分乘积值。操作模块对从第（N-1）PPG到第一PPG的输出进行总结操作，最后添加第N个PPG的输出。另外，由于前置零位检测器检测到乘法器或被乘数中的任何前导零位，所以对应于“0”位的部分积输出直接设置为零。

9. 发明申请

US20060242219A1 Asynchronous multiplier 审中-公开
标题翻译：异步乘法器
公开(公告)号：US20060242219A1
公开(公告)日：2006-10-26
申请号：US11111080
申请日：2005-04-20
申请人： Chin-Yung Chen , Kuang-Shyr Wu
发明人： Chin-Yung Chen , Kuang-Shyr Wu
IPC分类号： G06F7/52
CPC分类号： G06F7/5306 , G06F2207/3864
摘要： An asynchronous multiplier is provided. The multiplier comprises a partial product generator, an addition array, a leading-zero-bit detector, a final-stage adder and a completion detector. The partial product generator generates a plurality of partial products, and the addition array adds these partial products. The leading-zero-bit detector detects effective bits of the multiplicand and the multiplier, and outputs a set of detection signals so that the adder of the addition array determines either to output zero or perform addition operation. Then, the final-stage adder adds these partial products and outputs a sum. Finally, the completion detector checks and outputs the result.
摘要翻译：提供了一个异步乘法器。乘法器包括部分乘积发生器，加法阵列，前置零位检测器，最后级加法器和完成检测器。部分积发生器产生多个部分积，并且加法阵列添加这些部分乘积。前置零位检测器检测被乘数和乘法器的有效位，并输出一组检测信号，使得加法阵列的加法器确定输出为零或执行加法运算。然后，最后一级加法器将这些部分乘积相加并输出一个和。最后，完成检测器检查并输出结果。

10. 发明授权

US08766451B2 Chip packaging structure 有权
标题翻译：芯片封装结构
公开(公告)号：US08766451B2
公开(公告)日：2014-07-01
申请号：US13435770
申请日：2012-03-30
申请人： Chin-Yung Chen
发明人： Chin-Yung Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/4985 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1316 , H01L2224/1412 , H01L2224/16225 , H01L2924/00014 , H01L2924/00
摘要： A chip packaging structure includes a flexible plate, a chip, and a plurality of leads. The chip is disposed on the flexible plate. A first boundary and a second boundary are defined on the flexible plate. The first boundary is located between the chip and the second boundary. A first area is formed between the first boundary and the chip. A second area is formed between the first boundary and the second boundary. The chip includes a plurality of signal conducting points and a plurality of non-signal conducting points. The plurality of leads are disposed on the flexible plate and include a plurality of signal leads and a plurality of non-signal leads. The width of the non-signal lead is smaller than the width of the signal lead extending out of the second boundary.
摘要翻译：芯片封装结构包括柔性板，芯片和多个引线。芯片设置在柔性板上。在柔性板上限定第一边界和第二边界。第一个边界位于芯片和第二个边界之间。在第一边界和芯片之间形成第一区域。在第一边界和第二边界之间形成第二区域。芯片包括多个信号导通点和多个非信号导通点。多个引线设置在柔性板上，并且包括多个信号引线和多个非信号引线。非信号引线的宽度小于从第二边界延伸出来的信号引线的宽度。

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