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1. 发明授权

US5355114A Reconstruction of signals using redundant channels 失效
标题翻译：使用冗余通道重建信号
公开(公告)号：US5355114A
公开(公告)日：1994-10-11
申请号：US210065
申请日：1994-03-16
申请人： Philip H. Sutterlin , Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
发明人： Philip H. Sutterlin , Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
IPC分类号： H04B1/74 , H04B3/54 , H04L1/04 , H04M11/04
CPC分类号： H04B1/74 , H04B3/542 , H04L1/04 , H04B2203/5408 , H04B2203/5416 , H04B2203/5425 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495
摘要： In a power line communication apparatus, data is redundantly transmitted on a first and a second carrier where the carriers are separated by a predetermined number of Hz. In the receiver two channels are used, one for each of the carriers. The noise level in each channel is independently determined. A switching network is used to allow the selection of the channel with the lesser noise or if the noise is approximately equal in both channels, the signals in the channels are combined.
摘要翻译：在电力线通信装置中，数据在第一和第二载波上被冗余地发送，其中载波被隔开预定数量的Hz。在接收机中使用两个通道，每个载波一个。每个通道的噪声电平是独立确定的。交换网络用于允许以更小的噪声选择信道，或者如果两个信道中的噪声近似相等，则信道中的信号被组合。

2. 发明授权

US4529965A Switched-capacitor circuit analog-to-digital converter 失效
标题翻译：开关电容电路模数转换器
公开(公告)号：US4529965A
公开(公告)日：1985-07-16
申请号：US491217
申请日：1983-05-03
申请人： Chin-Chen Lee
发明人： Chin-Chen Lee
IPC分类号： H03F3/34 , H03F1/30 , H03F3/70 , H03M1/00 , H03M1/40 , H03K13/02
CPC分类号： H03F1/303 , H03M1/40
摘要： A switched-capacitor analog-to-digital converter implements a conversion scheme involving execution of an algorithmic technique of successive-approximation comprising a number of iterations dependent upon the conversion resolution desired. The algorithm used requires analog processing to produce an output voltage that is two times the output voltage resolved to realize the previous bit. The "times two" function is realized by adding the voltage of the last iteration to itself (i.e., V+V=2V). This is accomplished by storing the output voltage resolved into the previous bit and separately storing a voltage corresponding to that voltage. Both stored voltages are then transferred to an integrator circuit which adds the two voltages and produces the output voltage to be resolved into the next bit.
摘要翻译：开关电容器模数转换器实现涉及执行逐次逼近的算法技术的转换方案，其包括取决于所需转换分辨率的多次迭代。所使用的算法需要模拟处理，以产生输出电压的两倍，该输出电压被分辨为实现前一位的输出电压的两倍。通过将最后一次迭代的电压（即V + V = 2V）相加来实现“次”功能。这通过将分辨的输出电压存储到前一位并分别存储与该电压相对应的电压来实现。然后将两个存储的电压传送到积分器电路，该积分器电路将两个电压相加并产生要被分解为下一个位的输出电压。

3. 发明申请

US20130164971A1 SMART PLUGS, SMART SOCKETS AND SMART ADAPTORS 有权
标题翻译：智能插座，智能插座和智能适配器
公开(公告)号：US20130164971A1
公开(公告)日：2013-06-27
申请号：US13479183
申请日：2012-05-23
申请人： Shen-Ming Chung , Hsiao-Hui Lee , Chin-Chen Lee
发明人： Shen-Ming Chung , Hsiao-Hui Lee , Chin-Chen Lee
IPC分类号： H01R3/00
CPC分类号： H01R13/665 , G01R19/2513 , H01R31/065
摘要： A smart socket is provided. The smart socket has a set of power sockets, configured for a set of power pins of a smart plug to plug into, a driving pin and a set of detection pins, configured for forming a circuit with a set of feedback pins of a smart plug when the set of power pins is plugged into the power sockets, and an identification code module, configured for obtaining an identification code of an electric appliance, from the circuit, to which the smart plug belongs.
摘要翻译：提供智能插座。智能插座具有一组电源插座，配置用于插入智能插头的一组电源引脚，驱动引脚和一组检测引脚，配置为用智能插头的一组反馈引脚形成电路当所述一组电源插头插入到所述电源插座中时，以及识别码模块，被配置为从所述智能插头所属的电路获得电器的识别码。

4. 发明授权

US5404127A Power line communication while avoiding determinable interference harmonics 失效
标题翻译：电力线通信同时避免可测量的干扰谐波
公开(公告)号：US5404127A
公开(公告)日：1995-04-04
申请号：US167431
申请日：1993-12-13
申请人： Chin-Chen Lee , Howard W. Johnson , Philip H. Sutterlin
发明人： Chin-Chen Lee , Howard W. Johnson , Philip H. Sutterlin
IPC分类号： H04B3/54 , H04L27/18 , H04M11/04
CPC分类号： H04B3/542 , H04L27/18 , H04B2203/5416 , H04B2203/5425 , H04B2203/5445 , H04B2203/545 , H04B2203/5483 , H04B2203/5491
摘要： A power line communication (PLC) apparatus wherein a carrier is derived to avoid determinable interference harmonics. In order to transmit data on a power line containing the television interference or other determinable interference harmonics, the present invention uses redundant carriers at a frequency between the television interference harmonics. In the preferred embodiment, the first carrier is positioned at 118 KHz and the redundant carrier is positioned at 133.7 KHz for the PLC apparatus designed for use in the United States. Other carrier frequencies are used for other countries in order to avoid interference harmonics at a slightly different frequency. The present invention includes a waveshaping and modulation circuit for generating the modulated data waveform for output over the power line. In the preferred embodiment, the waveshaping and modulation circuit includes a waveshape ROM for storing samples that represent the appearance of the carrier waveshape. Once the appropriate waveshape is selected from the waveshape ROM, the 256 discrete points of the waveshape are clocked out an interface line to a DAC, a filter, an amplifier and on to a PLC coupling network for isolating and coupling the signal onto the power line. On the receive side, receive filters are used to separate the received data from determinable interference harmonics. These filters comprise four matched filters, two for each channel. These filters operate in cooperation with the waveshaping and modulation circuitry in order to capture the signals modulated between determinable interference harmonics such as television interference harmonics.
摘要翻译：一种电力线通信（PLC）装置，其中导出载波以避免可确定的干扰谐波。为了在包含电视干扰或其他可确定的干扰谐波的电力线上发送数据，本发明以电视干扰谐波之间的频率使用冗余载波。在优选实施例中，第一载体位于118KHz，冗余载体位于设计用于美国的PLC装置的133.7KHz。其他载波频率用于其他国家，以便以稍微不同的频率避免干扰谐波。本发明包括波形整形和调制电路，用于产生用于在电力线上输出的调制数据波形。在优选实施例中，波形整形和调制电路包括用于存储表示载波波形的外观的样本的波形ROM。一旦从波形ROM中选择了适当的波形，波形的256个离散点将时钟输出到DAC，滤波器，放大器的接口线，并连接到PLC耦合网络上，以将信号隔离并耦合到电源线。在接收侧，接收滤波器用于将接收的数据与可确定的干扰谐波分离。这些滤波器包括四个匹配滤波器，每个通道两个。这些滤波器与波形成形和调制电路协同操作，以便捕获在诸如电视干扰谐波之间的可确定的干扰谐波之间调制的信号。

5. 发明授权

US5210518A Apparatus and method for reducing errors in data caused by noise 失效
标题翻译：用于减少由噪声引起的数据中的错误的装置和方法
公开(公告)号：US5210518A
公开(公告)日：1993-05-11
申请号：US698600
申请日：1991-05-10
申请人： Martin H. Graham , Howard W. Johnson , Philip H. Sutterlin , Chin-Chen Lee , Amy O. Hurlbut
发明人： Martin H. Graham , Howard W. Johnson , Philip H. Sutterlin , Chin-Chen Lee , Amy O. Hurlbut
IPC分类号： H03G3/34 , H04B3/54
CPC分类号： H04B3/542 , H03G3/345 , H04B2203/5408 , H04B2203/5416 , H04B2203/5425 , H04B2203/5445 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495
摘要： In a power line communications apparatus an improvement for blanking or snubbing impulse noise. The impulse noise is detected and used to snub the detected signal. The duration of the snubbing pulses is controlled to assure complete blanking of noise including the trailing noise signals following a main noise pulse which may not otherwise be detectable. Also, the number of snubbing pulses which can occur are limited to prevent too much energy from being snubbed during any given baud period.
摘要翻译：在电力线通信装置中，消隐或缓冲脉冲噪声的改进。脉冲噪声被检测并用于缓冲检测到的信号。控制缓冲脉冲的持续时间以确保完全消隐噪声，包括主噪声脉冲之后的后续噪声信号，否则可能无法检测到。此外，可以发生的缓冲脉冲的数量被限制以防止在任何给定的波特周期期间太多的能量被阻塞。

6. 发明授权

US09231351B2 Smart plugs, smart sockets and smart adaptors 有权
标题翻译：智能插头，智能插座和智能适配器
公开(公告)号：US09231351B2
公开(公告)日：2016-01-05
申请号：US13479183
申请日：2012-05-23
申请人： Shen-Ming Chung , Hsiao-Hui Lee , Chin-Chen Lee
发明人： Shen-Ming Chung , Hsiao-Hui Lee , Chin-Chen Lee
IPC分类号： H01R3/00 , H01R13/66 , H01R31/06 , G01R19/25
CPC分类号： H01R13/665 , G01R19/2513 , H01R31/065
摘要： A smart socket is provided. The smart socket has a set of power sockets, configured for a set of power pins of a smart plug to plug into, a driving pin and a set of detection pins, configured for forming a circuit with a set of feedback pins of a smart plug when the set of power pins is plugged into the power sockets, and an identification code module, configured for obtaining an identification code of an electric appliance, from the circuit, to which the smart plug belongs.
摘要翻译：提供智能插座。智能插座具有一组电源插座，配置用于插入智能插头的一组电源引脚，驱动引脚和一组检测引脚，配置为用智能插头的一组反馈引脚形成电路当所述一组电源插头插入到所述电源插座中时，以及识别码模块，被配置为从所述智能插头所属的电路获取电器的识别码。

7. 发明授权

US5260974A Adaptive carrier detection 失效
标题翻译：自适应载波检测
公开(公告)号：US5260974A
公开(公告)日：1993-11-09
申请号：US698408
申请日：1991-05-10
申请人： Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
发明人： Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
IPC分类号： H04B1/10 , H04L25/06 , H03D1/04
CPC分类号： H04L25/062 , H04B1/1027 , H04B3/542 , H04B2203/5408 , H04B2203/5416 , H04B2203/5425 , H04B2203/5445 , H04B2203/5483 , H04B2203/5491 , H04B2203/5495
摘要： An improvement in an apparatus which uses a carrier detection threshold level for detecting a carrier signal modulated with binary data. The threshold level is dynamically changed and generally seeks a level above the background noise. The threshold level is maintained constant when the detected signal exceeds the threshold level. An evaluation circuit is able to examine the detected signal to determine whether it contains data or only noise, and if it contains only noise, a possible trapped condition is avoided by raising the threshold level to a level higher than the background noise.
摘要翻译：使用载波检测阈值电平检测用二进制数据调制的载波信号的装置的改进。阈值水平被动态地改变，并且通常寻求高于背景噪声的水平。当检测到的信号超过阈值电平时，阈值电平保持恒定。评估电路能够检查检测到的信号以确定其是否包含数据或仅包含噪声，并且如果它仅包含噪声，则可以通过将阈值电平提高到高于背景噪声的水平来避免可能的捕获状态。

8. 发明授权

US06742078B1 Management, data link structure and calculating method for flash memory 有权
标题翻译：闪存的管理，数据链路结构和计算方法
公开(公告)号：US06742078B1
公开(公告)日：2004-05-25
申请号：US09412323
申请日：1999-10-05
申请人： Cheng-Chih Chien , Chin-Chen Lee , Khein Seng Pua , Soo Ching Ng , Jiunn-Yeong Yang
发明人： Cheng-Chih Chien , Chin-Chen Lee , Khein Seng Pua , Soo Ching Ng , Jiunn-Yeong Yang
IPC分类号： G06F1200
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0679 , G06F12/0246 , G06F2212/7207 , G11C29/76
摘要： The present invention relates to a management and link structure of a flash memory. The flash memory is divided into several different types of data access blocks, such as general data blocks, spare blocks, link-table block, and new blocks. A simple data link structure is provided, and a management and calculating method for spare blocks saves time to search and write data effectively and prolongs the service life of the flash memory.
摘要翻译：本发明涉及闪速存储器的管理和链接结构。闪存被分为几种不同类型的数据访问块，例如通用数据块，备用块，链接表块和新块。提供简单的数据链路结构，并且备用块的管理和计算方法有效地节省了搜索和写入数据的时间，并延长了闪存的使用寿命。

9. 发明授权

US5289476A Transmission mode detection in a modulated communication system 失效
标题翻译：调制通信系统中的传输模式检测
公开(公告)号：US5289476A
公开(公告)日：1994-02-22
申请号：US698445
申请日：1991-05-10
申请人： Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
发明人： Howard W. Johnson , Chin-Chen Lee , Amy O. Hurlbut
IPC分类号： H04B3/54 , H04L1/00 , H04L27/00 , C06F11/10 , H03D3/22 , H04L27/20
CPC分类号： H04L1/0039 , H04B3/542 , H04L1/0003 , H04L1/0025 , H04L1/0029 , H04L1/0072 , H04L27/0012 , H04B2203/5408 , H04B2203/5416 , H04B2203/5445 , H04B2203/5483 , H04L1/0057
摘要： A power line communication (PLC) apparatus wherein transmission mode information is encoded into each data packet while maintaining immunity from single bit errors. In the present invention, a power line communication system includes a transmitter/receiver (i.e. transceiver) which is coupled to a power distribution network. Data is transmitted through the power line by the transceiver in packets. The transceiver includes a preamble generator which creates a preamble for each of the data packets and a preamble decoder that decodes the preamble of a data packet and determines word sync for the packet. The preamble generated by the preamble generator consists of a carrier detect interval, a carrier sync interval, a bit sync interval, and a word sync pattern. The transceiver may select either BPSK or QPSK transmission modes on a data packet by data packet basis by encoding information into the packet preamble. Transmission mode information is encoded into the preamble using one of two seven-bit cross compatible word sync patterns for each data packet. Thus, one word sync pattern is used to define a BPSK transmission while the other word sync pattern is used to define a QPSK transmission. The transmitter may send data packets using either BPSK or QPSK on a packet by packet basis by generating the appropriate word sync pattern for each packet. The receiver uses the word sync pattern to determine the receive mode for each packet.
摘要翻译：一种电力线通信（PLC）装置，其中传输模式信息被编码到每个数据包中，同时保持对单个位错误的抵抗。在本发明中，电力线通信系统包括耦合到配电网络的发射机/接收机（即，收发机）。数据通过收发器在数据包中通过电力线传输。收发器包括前导码生成器，其为每个数据分组创建前同步码，以及解码数据分组的前同步码并确定该分组的单词同步的前导解码器。由前导码生成器产生的前导码由载波检测间隔，载波同步间隔，位同步间隔和字同步模式组成。收发器可以通过数据分组来选择数据分组上的BPSK或QPSK传输模式，通过将信息编码到分组前同步码中。使用针对每个数据分组的两个七位交叉兼容字同步模式之一将传输模式信息编码到前导码中。因此，一个字同步模式用于定义BPSK传输，而另一个字同步模式用于定义QPSK传输。发送器可以通过基于分组的方式使用BPSK或QPSK来发送数据分组，通过为每个分组生成适当的字同步模式。接收机使用字同步模式来确定每个数据包的接收模式。

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