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1. 发明申请

US20100165704A1 Circuit and Method for a High Speed Memory Cell 有权
标题翻译：高速存储器单元的电路和方法
公开(公告)号：US20100165704A1
公开(公告)日：2010-07-01
申请号：US12346173
申请日：2008-12-30
申请人： Cheng-Hsu Wu , David Yen , Tsai-Hsin Lai
发明人： Cheng-Hsu Wu , David Yen , Tsai-Hsin Lai
IPC分类号： G11C11/24 , G11C11/416
CPC分类号： G11C11/416 , G11C11/405
摘要： A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.
摘要翻译：公开了一种存储器单元，包括耦合在存储节点和写位线之间的写入存取晶体管，并且在写入周期期间响应于写入字线上的电压而有效; 读取存取晶体管，耦合在读取字线和读取位线之间，并且响应于存储节点处的电压在读取周期期间有效; 以及耦合在读取字线和存储节点之间的存储电容器。还公开了用于操作存储器单元的方法。

2. 发明授权

US07566935B2 ESD structure without ballasting resistors 有权
标题翻译： ESD结构，无镇流电阻
公开(公告)号：US07566935B2
公开(公告)日：2009-07-28
申请号：US11713193
申请日：2007-03-01
申请人： Shu Huei Lin , Jian Hsing Lee , Shao Chang Huang , Cheng Hsu Wu , Chuan Ying Lee
发明人： Shu Huei Lin , Jian Hsing Lee , Shao Chang Huang , Cheng Hsu Wu , Chuan Ying Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.
摘要翻译：一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域在第一N阱之外，但是在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远从第一个Nwell比NMOS晶体管。

3. 发明授权

US06428736B1 Method for forming a hollow bottom of acrylic cups 失效
标题翻译：形成丙烯酸杯的中空底部的方法
公开(公告)号：US06428736B1
公开(公告)日：2002-08-06
申请号：US09371851
申请日：1999-08-11
申请人： Cheng-Hsu Wu
发明人： Cheng-Hsu Wu
IPC分类号： B29D2400
CPC分类号： B29C45/1704 , B29C45/0053 , B29C45/38 , B29C45/7207 , B29C69/02 , B29C2045/1715 , B29L2031/7132
摘要： A method for forming a hollow bottom of an acrylic cup by forming a cup body by injecting a molding with a liquid transparent or semi-transparent acrylic material into a mold to form a mushroom shaped cavity. The cavity in the bottom of the cup body is filled with a gas, permitting the whole cup to appear to have a three dimensional (3D) visual effect. The cavity of the bottom of the cup can be filled with a non-colored or colored liquid to permit the whole cup to contain a deflected visual effect of a plurality of colored layers.
摘要翻译：一种用于通过将具有液体透明或半透明丙烯酸材料的模制件注射到模具中以形成蘑菇形腔体而形成杯体的方法来形成丙烯酸杯的中空底部的方法。杯体底部的空腔充满气体，允许整个杯子看起来具有三维（3D）视觉效果。杯底部的空腔可以填充无色或有色液体，以允许整个杯子包含多个着色层的偏转的视觉效果。

4. 发明授权

US06281061B1 Method for fabricating an isolation trench applied in BiCMOS processes 有权
标题翻译：用于制造应用于BiCMOS工艺中的隔离沟槽的方法
公开(公告)号：US06281061B1
公开(公告)日：2001-08-28
申请号：US09575566
申请日：2000-05-22
申请人： Cheng-Hsu Wu , Chin Liang Chen
发明人： Cheng-Hsu Wu , Chin Liang Chen
IPC分类号： H01L218238
CPC分类号： H01L21/8249 , H01L21/76224
摘要： The present invention discloses a method for fabricating isolation trenches applied in BiCMOS processes. The isolation trenches are formed initially by defining an oxide layer formed on a semiconductor substrate. Then an epitaxy layer is formed on the substrate and a polysilicon layer is formed on the oxide layer by selective epitaxial growth (SEG). After forming well regions and a collector region in the epitaxy layer, the polysilicon layer is etched and stopped at the oxide layer such that trenches are formed. Subsequently, an isolating material is filled into the trenches to form isolation trenches. It is noted that the oxide layer definition, the epitaxy layer and the polysilicon layer growth by SEG, and the polysilicon etching processes simplify the process of forming isolation trenches. In addition, the integration of the semiconductor is increased, and the isolating effect is good.
摘要翻译：本发明公开了一种用于制造应用于BiCMOS工艺的隔离沟槽的方法。首先通过限定形成在半导体衬底上的氧化物层来形成隔离沟槽。然后在衬底上形成外延层，并通过选择性外延生长（SEG）在氧化物层上形成多晶硅层。在外延层中形成阱区域和集电极区域之后，在氧化物层处蚀刻并停止多晶硅层，从而形成沟槽。随后，将隔离材料填充到沟槽中以形成隔离沟槽。应注意，通过SEG的氧化物层定义，外延层和多晶硅层生长以及多晶硅蚀刻工艺简化了形成隔离沟槽的工艺。此外，半导体的集成增加，隔离效果良好。

5. 发明授权

US08009459B2 Circuit for high speed dynamic memory 有权
标题翻译：高速动态存储器电路
公开(公告)号：US08009459B2
公开(公告)日：2011-08-30
申请号：US12346173
申请日：2008-12-30
申请人： Cheng-Hsu Wu , David Yen , Tsai-Hsin Lai
发明人： Cheng-Hsu Wu , David Yen , Tsai-Hsin Lai
IPC分类号： G11C11/24
CPC分类号： G11C11/416 , G11C11/405
摘要： A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.
摘要翻译：存储单元包括耦合在存储节点和写位线之间的写入存取晶体管，并且响应于写字线上的电压在写周期期间有效; 读取存取晶体管，耦合在读取字线和读取位线之间，并且响应于存储节点处的电压在读取周期期间有效; 以及耦合在读取字线和存储节点之间的存储电容器。还公开了用于操作存储器单元的方法。

6. 发明申请

US20080211027A1 ESD structure without ballasting resistors 有权
标题翻译： ESD结构，无镇流电阻
公开(公告)号：US20080211027A1
公开(公告)日：2008-09-04
申请号：US11713193
申请日：2007-03-01
申请人： Shu Huei Lin , Jian-Hsing Lee , Shao-Chang Huang , Cheng Hsu Wu , Chuan Ying Lee
发明人： Shu Huei Lin , Jian-Hsing Lee , Shao-Chang Huang , Cheng Hsu Wu , Chuan Ying Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.
摘要翻译：一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域在第一N阱之外，但在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远从第一个Nwell比NMOS晶体管。

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