会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes
    • 用于薄膜晶体管和相关掺杂过程的轻掺杂漏极中的两个掺杂区域
    • US20140061656A1
    • 2014-03-06
    • US13601535
    • 2012-08-31
    • Cheng-Ho YuYoung Bae ParkShih Chang Chang
    • Cheng-Ho YuYoung Bae ParkShih Chang Chang
    • H01L27/15H01L33/08
    • H01L29/78621H01L27/1288H01L29/78645H01L29/78696
    • A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.
    • 提供了一种制造用于具有像素阵列的LCD的薄膜晶体管(TFT)的方法。 该方法包括在包括导电栅极层的TFT堆叠的一部分上沉积第一光致抗蚀剂层和半导体层。 该方法还包括以第一掺杂剂量掺杂暴露的半导体层。 该方法还包括蚀刻导电栅极层的一部分以暴露半导体层的一部分,并以第二掺杂剂量掺杂半导体层的暴露部分。 该方法还包括在像素的有源区域中在掺杂半导体层的第一部分上沉积第二光致抗蚀剂层,以在有源区域周围的区域中暴露掺杂半导体层的第二部分,以及掺杂半导体层的第二部分 掺杂半导体层具有第三掺杂剂量。
    • 6. 发明申请
    • Measuring System and Method
    • 测量系统和方法
    • US20090074154A1
    • 2009-03-19
    • US12211264
    • 2008-09-16
    • Wei-Cheng LinCheng-Ho Yu
    • Wei-Cheng LinCheng-Ho Yu
    • H04M1/24
    • G01R31/002
    • A measuring system comprises a pulse generator, an under test device, a variable resistor and a detecting control system. The pulse generator provides pulse signals with different voltage peaks to the under test device and the variable resistor. The variable resistor adjusts its resistance value according to a control signal. The detecting control system detects the voltage ringing ranges of the first terminal of the under test device at different resistance values. The detecting control system generates the control signal to adjust the resistance value of the variable resistor according to the voltage ringing ranges.
    • 测量系统包括脉冲发生器,被测装置,可变电阻器和检测控制系统。 脉冲发生器向下测试装置和可变电阻器提供具有不同电压峰值的脉冲信号。 可变电阻根据控制信号调整其电阻值。 检测控制系统以不同的电阻值检测被测装置的第一端子的电压振铃范围。 检测控制系统产生控制信号,根据电压振铃范围调整可变电阻的电阻值。
    • 7. 发明授权
    • Two doping regions in lightly doped drain for thin film transistors and associated doping processes
    • 用于薄膜晶体管和相关掺杂工艺的轻掺杂漏极中的两个掺杂区域
    • US08987027B2
    • 2015-03-24
    • US13601535
    • 2012-08-31
    • Cheng-Ho YuYoung Bae ParkShih Chang Chang
    • Cheng-Ho YuYoung Bae ParkShih Chang Chang
    • H01L21/00H01L29/786H01L27/12
    • H01L29/78621H01L27/1288H01L29/78645H01L29/78696
    • A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.
    • 提供了一种制造用于具有像素阵列的LCD的薄膜晶体管(TFT)的方法。 该方法包括在包括导电栅极层的TFT堆叠的一部分上沉积第一光致抗蚀剂层和半导体层。 该方法还包括以第一掺杂剂量掺杂暴露的半导体层。 该方法还包括蚀刻导电栅极层的一部分以暴露半导体层的一部分,并以第二掺杂剂量掺杂半导体层的暴露部分。 该方法还包括在像素的有源区域中在掺杂半导体层的第一部分上沉积第二光致抗蚀剂层,以在有源区域周围的区域中暴露掺杂半导体层的第二部分,以及掺杂半导体层的第二部分 掺杂半导体层具有第三掺杂剂量。