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1. 发明申请

US20130163336A1 Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory 有权
标题翻译：通过控制选择栅极电压擦除操作，用于3D非易失性存储器
公开(公告)号：US20130163336A1
公开(公告)日：2013-06-27
申请号：US13332844
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa , Chenfeng Zhang
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以用擦除电压来升高选择栅极电压，以避免导致退化的选择栅极之间的过多的漏极 - 栅极电压。选择栅极电压的升高可以从擦除操作的第一次擦除验证迭代开始，或者以预定或自适应确定的擦除验证迭代（例如基于编程擦除周期的数量）开始。

2. 发明申请

US20050042308A1 Pharmaceutical composition having cholagogic and litholytic effect and its preparation method 审中-公开
标题翻译：具有胆酸和岩石效应的药物组合物及其制备方法
公开(公告)号：US20050042308A1
公开(公告)日：2005-02-24
申请号：US10494143
申请日：2002-09-05
申请人： Wei Xiao , Yin Yang , Ya Ling , Minghui Li , Zhenggen Liao , Chenfeng Zhang , Shubo Cao
发明人： Wei Xiao , Yin Yang , Ya Ling , Minghui Li , Zhenggen Liao , Chenfeng Zhang , Shubo Cao
IPC分类号： G01N33/15 , A61K36/00 , A61K36/185 , A61K36/315 , A61K36/355 , A61K36/534 , A61K36/539 , A61K36/87 , A61P1/16 , A61P21/00 , A61P21/02 , A61P25/04 , A61P29/00 , A61P31/00 , A61P31/04 , G01N30/88 , G01N30/90 , A61K35/78
CPC分类号： A61K36/185 , A61K36/315 , A61K36/355 , A61K36/534 , A61K36/539 , A61K2300/00
摘要： The invention publishes a kind of drug complex with cholagogue and lithontriptic effect and its preparation method; the invention also publishes a kind of quality-control method of a kind of drug complex soft capsule. The invention drug complex is composed by the main materials of mint oil and herit oil. The aforementioned drug is mixed uniformly according to certain proportion, and can be added into conventional accessories to prepare into clinically accepted forms of drug, such as pill, tablet, orally-taken liquid preparation, capsule, granule et al. To control the drug quality according to the quality-control method of the soft-capsule-form drug publicized in the invention, good product stability and high repeatability can be acquired; The invention drug complex has distinct cholagogue, lithontriptic, anti-inflammation, analgesic effect through the pharmacological experiment.
摘要翻译：本发明公开了一种具有胆碱和药物作用的药物复合物及其制备方法; 本发明还公开了一种药物复合软胶囊的一种质量控制方法。本发明药物复合体由薄荷油和乳酸油的主要成分组成。上述药物按一定比例均匀混合，可加入常规配件中，制备成临床接受的药物，如丸剂，片剂，口服液制剂，胶囊剂，颗粒剂等。根据本发明公开的软胶囊形式药物的质量控制方法控制药物质量，可以获得良好的产品稳定性和高重复性; 本发明药物复合物通过药理实验具有明显的胆碱，溶栓，抗炎，镇痛作用。

3. 发明授权

US08908435B2 Erase operation with controlled select gate voltage for 3D non-volatile memory 有权
公开(公告)号：US08908435B2
公开(公告)日：2014-12-09
申请号：US13332844
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa , Chenfeng Zhang
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.

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