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    • 3. 发明申请
    • Packet Filter Optimization For Network Interfaces
    • 网络接口的数据包过滤器优化
    • US20100106874A1
    • 2010-04-29
    • US12260061
    • 2008-10-28
    • Charles DominguezBrian Tucker
    • Charles DominguezBrian Tucker
    • G06F13/24
    • G06F13/385G06F13/24Y02D10/14Y02D10/151
    • A method and apparatus to reduce the transaction overhead involved with packet I/O on a host bus without sacrificing the latency of packets of important traffic types is described. This involves determining whether a packet is to be aggregated in response to receiving the packet in a receive buffer. If it is determined that the packet should not be aggregated, a host system may be interrupted to indicate availability of the received packet. Subsequently, the packet may be forwarded to an interrupted system via a local bus directly from a receiving buffer without being stored in a local storage. If it is determined that a packet is to be aggregated, it may be stored in a queue in local storage. Subsequently, it may be sent to a host system with a group of other frames using a single bus transaction to eliminate overhead.
    • 描述了一种在主机总线上减少与分组I / O相关的事务开销而不牺牲重要业务类型的分组的等待时间的方法和装置。 这涉及确定在接收缓冲器中接收到分组时是否要聚合分组。 如果确定分组不应该被聚合,则主机系统可能被中断以指示所接收分组的可用性。 随后,分组可以经由本地总线直接从接收缓冲器转发到中断的系统,而不被存储在本地存储器中。 如果确定要聚合分组,则可以将其存储在本地存储器中的队列中。 随后,可以使用单个总线事务将其发送到具有一组其他帧的主机系统以消除开销。
    • 5. 发明授权
    • Multiple synchronous IQ demodulators
    • 多个同步IQ解调器
    • US08817936B2
    • 2014-08-26
    • US13478790
    • 2012-05-23
    • David Charles Dominguez
    • David Charles Dominguez
    • H04L7/00
    • H04L27/3818H03D3/007
    • A system for synchronizing IQ demodulators includes IQ demodulators, phase-controlling devices, a reference signal, a phase detector, and a control device. The phase-controlling devices are each associated with one of the IQ demodulators for outputting an output signal to its associated IQ demodulator having a phase controlled by the associated phase-controlling device. The phase detector is in communication with the output signals for determining whether the phase of any of the output signals is out-of-phase with a reference phase of the reference signal. The control-device is in communication with the phase-controlling devices programmed, internally or externally, to send a control signal to the associated phase-controlling device for any of the output signals which are out-of-phase with the reference phase of the reference signal so that the associated phase-controlling device synchronizes the phase of the output signal to being in-phase with the reference phase of the reference signal.
    • 用于IQ解调器同步的系统包括IQ解调器,相位控制装置,参考信号,相位检测器和控制装置。 相位控制装置各自与IQ解调器中的一个相关联,用于将输出信号输出到其相关联的IQ解调器,其具有由相关联的相位控制装置控制的相位。 相位检测器与输出信号通信,用于确定任何输出信号的相位是否与参考信号的参考相位不相位。 控制装置与内部或外部编程的相位控制装置进行通信,以向与相关联的相位控制装置发送控制信号,用于任何输出信号,该输出信号与 使得相关联的相位控制装置将输出信号的相位与参考信号的参考相位同相。
    • 6. 发明申请
    • MULTIPLE SYNCHRONOUS IQ DEMODULATORS
    • 多个同步智商解调器
    • US20130315289A1
    • 2013-11-28
    • US13478790
    • 2012-05-23
    • David Charles Dominguez
    • David Charles Dominguez
    • H04L27/22H04L27/01
    • H04L27/3818H03D3/007
    • A system for synchronizing IQ demodulators includes IQ demodulators, phase-controlling devices, a reference signal, a phase detector, and a control device. The phase-controlling devices are each associated with one of the IQ demodulators for outputting an output signal to its associated IQ demodulator having a phase controlled by the associated phase-controlling device. The phase detector is in communication with the output signals for determining whether the phase of any of the output signals is out-of-phase with a reference phase of the reference signal. The control-device is in communication with the phase-controlling devices programmed, internally or externally, to send a control signal to the associated phase-controlling device for any of the output signals which are out-of-phase with the reference phase of the reference signal so that the associated phase-controlling device synchronizes the phase of the output signal to being in-phase with the reference phase of the reference signal.
    • 用于IQ解调器同步的系统包括IQ解调器,相位控制装置,参考信号,相位检测器和控制装置。 相位控制装置各自与IQ解调器中的一个相关联,用于将输出信号输出到其相关联的IQ解调器,其具有由相关联的相位控制装置控制的相位。 相位检测器与输出信号通信,用于确定任何输出信号的相位是否与参考信号的参考相位不相位。 控制装置与内部或外部编程的相位控制装置进行通信,以向与相关联的相位控制装置发送控制信号,用于任何输出信号,该输出信号与 使得相关联的相位控制装置将输出信号的相位与参考信号的参考相位同相。