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1. 发明授权

US08732226B2 Integer rounding operation 有权
标题翻译：整数舍入操作
公开(公告)号：US08732226B2
公开(公告)日：2014-05-20
申请号：US11447344
申请日：2006-06-06
申请人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
发明人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
IPC分类号： G06F7/38 , G06F7/499
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49915 , G06F7/49963 , G06F9/30014 , G06F9/30036
摘要： Systems, methods, processors, media, and other embodiments associated with integer rounding a floating point number in one micro-operation (uop) are described. One system embodiment includes a memory to store an integer rounding floating point instruction and a processor to perform the integer rounding floating point instruction. The processor may include a floating point unit that includes circuits and/or logics that integer round the floating point number.
摘要翻译：描述了在一个微操作（uop）中与整数舍入浮点数相关联的系统，方法，处理器，介质和其他实施例。一个系统实施例包括存储整数舍入浮点指令的存储器和执行整数舍入浮点指令的处理器。处理器可以包括浮点单元，其包括围绕浮点数整数的电路和/或逻辑。

2. 发明申请

US20130268794A1 REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT OF A PROCESSOR 有权
标题翻译：在加热器的加热多功能（FMA）单元中降低功耗
公开(公告)号：US20130268794A1
公开(公告)日：2013-10-10
申请号：US13993370
申请日：2011-11-21
申请人： Chad D. Hancock
发明人： Chad D. Hancock
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F7/57 , G06F1/3206 , G06F1/3234 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/509 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/30036 , Y02D10/171 , Y02D10/24
摘要： In one embodiment, the present invention includes a processor having a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions. This unit can include an adder with multiple segments each independently controlled by a logic. The logic can clock gate at least one segment during execution of an add-like instruction in another segment of the adder when the add-like instruction has a width less than a width of the FMA unit. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有融合乘法（FMA）单元以执行FMA指令和类似附加指令的处理器。该单元可以包括具有多个段的加法器，每个段由逻辑单独地控制。当附加样指令的宽度小于FMA单元的宽度时，逻辑可以在加法器的另一段中执行附加类指令期间对至少一个段进行时钟门控。描述和要求保护其他实施例。

3. 发明申请

US20070282938A1 Integer rounding operation 有权
标题翻译：整数舍入操作
公开(公告)号：US20070282938A1
公开(公告)日：2007-12-06
申请号：US11447344
申请日：2006-06-06
申请人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
发明人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49915 , G06F7/49963 , G06F9/30014 , G06F9/30036
摘要： Systems, methods, processors, media, and other embodiments associated with integer rounding a floating point number in one micro-operation (uop) are described. One system embodiment includes a memory to store an integer rounding floating point instruction and a processor to perform the integer rounding floating point instruction. The processor may include a floating point unit that includes circuits and/or logics that integer round the floating point number.
摘要翻译：描述了在一个微操作（uop）中与整数舍入浮点数相关联的系统，方法，处理器，介质和其他实施例。一个系统实施例包括存储整数舍入浮点指令的存储器和执行整数舍入浮点指令的处理器。处理器可以包括浮点单元，其包括围绕浮点数整数的电路和/或逻辑。

4. 发明授权

US09360920B2 Reducing power consumption in a fused multiply-add (FMA) unit of a processor 有权
标题翻译：降低处理器的融合乘法（FMA）单元中的功耗
公开(公告)号：US09360920B2
公开(公告)日：2016-06-07
申请号：US13993370
申请日：2011-11-21
申请人： Chad D. Hancock
发明人： Chad D. Hancock
IPC分类号： G06F1/32 , G06F9/305 , G06F7/483 , G06F9/30 , G06F7/544 , G06F7/57 , G06F7/509
CPC分类号： G06F7/57 , G06F1/3206 , G06F1/3234 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/509 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/30036 , Y02D10/171 , Y02D10/24
摘要： In one embodiment, the present invention includes a processor having a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions. This unit can include an adder with multiple segments each independently controlled by a logic. The logic can clock gate at least one segment during execution of an add-like instruction in another segment of the adder when the add-like instruction has a width less than a width of the FMA unit. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有融合乘法（FMA）单元以执行FMA指令和类似附加指令的处理器。该单元可以包括具有多个段的加法器，每个段由逻辑单独地控制。当附加样指令的宽度小于FMA单元的宽度时，逻辑可以在加法器的另一段中执行附加类指令期间对至少一个段进行时钟门控。描述和要求保护其他实施例。

5. 发明申请

US20140108480A1 APPARATUS AND METHOD FOR VECTOR COMPUTE AND ACCUMULATE 审中-公开
标题翻译：用于矢量计算和累积的装置和方法
公开(公告)号：US20140108480A1
公开(公告)日：2014-04-17
申请号：US13994090
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Martin G Dixon , Kshitij A Doshi , James C Abel , Maxim Loktyukhin , Chad D Hancock , Michael A Julier , Navin Vemuri
发明人： Elmoustapha Ould-Ahmed-Vall , Martin G Dixon , Kshitij A Doshi , James C Abel , Maxim Loktyukhin , Chad D Hancock , Michael A Julier , Navin Vemuri
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F9/3001 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： An apparatus and method are described for comparing elements between two immediate values. For example, a method according to one embodiment includes the following operations: reading values of a first set of elements stored in a first immediate value, each element having a defined element position in the first immediate value; comparing each element from the first set of elements with each of a second set of elements stored in a second immediate value; counting the number of times the value of each element of the first set of elements is found in the second set of elements to arrive at a final count for each element of the first set of elements; and transferring the final count for each element to a third immediate value, wherein the final count is stored in an element position in the third immediate value corresponding to the defined element position in the first immediate value.
摘要翻译：描述了用于比较两个立即值之间的元素的装置和方法。例如，根据一个实施例的方法包括以下操作：读取存储在第一立即值中的第一组元素的值，每个元素在第一立即值中具有定义的元素位置; 将来自第一组元素的每个元素与存储在第二立即值中的第二组元素进行比较; 对在第二组元素中找到第一组元素的每个元素的值的次数进行计数，以得到第一组元素的每个元素的最终计数; 以及将每个元素的最终计数转移到第三立即值，其中最终计数被存储在与第一立即值中定义的元素位置对应的第三立即值中的元素位置中。

6. 发明申请

US20130339689A1 LATER STAGE READ PORT REDUCTION 审中-公开
标题翻译：后期阅读端口减少
公开(公告)号：US20130339689A1
公开(公告)日：2013-12-19
申请号：US13993546
申请日：2011-12-29
申请人： Srikanth T. Srinivasan , Chia Yin Kevin Lai , Bambang Sutanto , Chad D. Hancock
发明人： Srikanth T. Srinivasan , Chia Yin Kevin Lai , Bambang Sutanto , Chad D. Hancock
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30141 , G06F9/3828
摘要： In some implementations, a register file has a plurality of read ports for providing data to a micro-operation during execution of the micro-operation. For example, the micro-operation may utilize at least two data sources, with at least one first data source being utilized at least one pipeline stage earlier than at least one second data source. A number of register file read ports may be allocated for executing the micro-operation. A bypass calculation is performed during a first pipeline stage to detect whether the at least one second data source is available from a bypass network. During a subsequent second pipeline stage, when the at least one second data source is detected to be available from the bypass network, the number of the read ports allocated to the micro-operation may be reduced.
摘要翻译：在一些实现中，寄存器文件具有多个读端口，用于在执行微操作期间向微操作提供数据。例如，微操作可以利用至少两个数据源，其中至少一个第一数据源被使用在比至少一个第二数据源更早的至少一个流水线级。可以分配多个寄存器文件读取端口用于执行微操作。在第一流水线阶段期间执行旁路计算，以检测至少一个第二数据源是否可用于旁路网络。在随后的第二流水线阶段期间，当检测到至少一个第二数据源从旁路网络可用时，可以减少分配给微操作的读取端口的数量。

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