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1. 发明授权

US08732226B2 Integer rounding operation 有权
标题翻译：整数舍入操作
公开(公告)号：US08732226B2
公开(公告)日：2014-05-20
申请号：US11447344
申请日：2006-06-06
申请人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
发明人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
IPC分类号： G06F7/38 , G06F7/499
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49915 , G06F7/49963 , G06F9/30014 , G06F9/30036
摘要： Systems, methods, processors, media, and other embodiments associated with integer rounding a floating point number in one micro-operation (uop) are described. One system embodiment includes a memory to store an integer rounding floating point instruction and a processor to perform the integer rounding floating point instruction. The processor may include a floating point unit that includes circuits and/or logics that integer round the floating point number.
摘要翻译：描述了在一个微操作（uop）中与整数舍入浮点数相关联的系统，方法，处理器，介质和其他实施例。一个系统实施例包括存储整数舍入浮点指令的存储器和执行整数舍入浮点指令的处理器。处理器可以包括浮点单元，其包括围绕浮点数整数的电路和/或逻辑。

2. 发明申请

US20070282938A1 Integer rounding operation 有权
标题翻译：整数舍入操作
公开(公告)号：US20070282938A1
公开(公告)日：2007-12-06
申请号：US11447344
申请日：2006-06-06
申请人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
发明人： Mohammad Abdallah , Chad D. Hancock , Kwok W. Lui
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49915 , G06F7/49963 , G06F9/30014 , G06F9/30036
摘要： Systems, methods, processors, media, and other embodiments associated with integer rounding a floating point number in one micro-operation (uop) are described. One system embodiment includes a memory to store an integer rounding floating point instruction and a processor to perform the integer rounding floating point instruction. The processor may include a floating point unit that includes circuits and/or logics that integer round the floating point number.
摘要翻译：描述了在一个微操作（uop）中与整数舍入浮点数相关联的系统，方法，处理器，介质和其他实施例。一个系统实施例包括存储整数舍入浮点指令的存储器和执行整数舍入浮点指令的处理器。处理器可以包括浮点单元，其包括围绕浮点数整数的电路和/或逻辑。

3. 发明授权

US10360031B2 Fast unaligned memory access 有权
公开(公告)号：US10360031B2
公开(公告)日：2019-07-23
申请号：US14376825
申请日：2011-10-21
申请人： Mandeep Singh , Mohammad Abdallah
发明人： Mandeep Singh , Mohammad Abdallah
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F13/16 , G06F12/0888
摘要： Fast unaligned memory access. In accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

4. 发明授权

US09766893B2 Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines 有权
公开(公告)号：US09766893B2
公开(公告)日：2017-09-19
申请号：US13428440
申请日：2012-03-23
申请人： Mohammad Abdallah
发明人： Mohammad Abdallah
IPC分类号： G06F9/50 , G06F9/30 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3009 , G06F9/30105 , G06F9/30123 , G06F9/34 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/5038 , G06F9/5077 , G06F2209/506 , Y02D10/22 , Y02D10/36
摘要： A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.

5. 发明申请

US20170262287A1 SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH PREDICTION 审中-公开
公开(公告)号：US20170262287A1
公开(公告)日：2017-09-14
申请号：US13824013
申请日：2011-09-16
申请人： Mohammad Abdallah
发明人： Mohammad Abdallah
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3806 , G06F9/30018 , G06F9/30029 , G06F9/30047 , G06F9/3804 , G06F9/3836 , G06F9/3844 , G06F9/3869 , G06F12/0875 , G06F2212/1016 , G06F2212/452
摘要： A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

6. 发明授权

US09678755B2 Instruction sequence buffer to enhance branch prediction efficiency 有权
公开(公告)号：US09678755B2
公开(公告)日：2017-06-13
申请号：US13879365
申请日：2011-10-12
申请人： Mohammad Abdallah
发明人： Mohammad Abdallah
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30058 , G06F9/3808 , G06F9/3844
摘要： A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.

7. 发明授权

US09542187B2 Guest instruction block with near branching and far branching sequence construction to native instruction block 有权
标题翻译：访客指令块，具有近分支和远分支序列构造到本地指令块
公开(公告)号：US09542187B2
公开(公告)日：2017-01-10
申请号：US13359817
申请日：2012-01-27
申请人： Mohammad Abdallah
发明人： Mohammad Abdallah
IPC分类号： G06F9/45 , G06F9/32 , G06F9/30 , G06F9/38 , G06F9/455
CPC分类号： G06F9/322 , G06F9/30058 , G06F9/30174 , G06F9/3808 , G06F9/3844 , G06F9/3863 , G06F9/4552
摘要： A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.
摘要翻译：一种用于翻译处理器的指令的方法。该方法包括：访问包括至少一个来宾远分支的多个客运分支指令的多个访客指令，以及通过在至少一个来宾远分支上使用分支预测来从多个访客指令构建指令序列。所述方法还包括从所述指令序列组装来宾指令块。访客指令块被转换为相应的本机转换块，其中对应于至少一个来宾远分支的至少一个本地远分支，并且其中所述至少一个本地远分支包括用于相对分支路径的相对的访客地址的至少一个客户远分支。在遇到错误预测时，通过访问相对的访客地址获得正确的指令序列。

8. 发明授权

US09442772B2 Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines 有权
标题翻译：全局和局部互连结构包括路由矩阵以支持多个引擎执行指令序列
公开(公告)号：US09442772B2
公开(公告)日：2016-09-13
申请号：US13475739
申请日：2012-05-18
申请人： Mohammad Abdallah
发明人： Mohammad Abdallah
IPC分类号： G06F9/50 , G06F15/80 , G06F9/38 , G06F9/30 , G06F9/52 , G06F9/48 , G06F9/46
CPC分类号： G06F9/5077 , G06F9/3012 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3891 , G06F9/46 , G06F9/4881 , G06F9/52 , G06F13/4068 , G06F15/80
摘要： A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.
摘要翻译：全球互连系统。全局互连系统包括具有用于支持多个代码序列的执行的数据的多个资源和用于实现多个代码序列的执行的多个引擎。多个资源消耗者在多个发动机的每一个内。全局互连结构耦合到多个资源使用者，并耦合到多个资源，以实现多个代码序列的数据访问和执行，其中资源使用者通过全局互连结构的每周期利用来访问资源。

9. 发明授权

US09424046B2 Systems and methods for load canceling in a processor that is connected to an external interconnect fabric 有权
标题翻译：连接到外部互连结构的处理器中负载消除的系统和方法
公开(公告)号：US09424046B2
公开(公告)日：2016-08-23
申请号：US13649505
申请日：2012-10-11
申请人： Karthikeyan Avudaiyappan , Mohammad Abdallah
发明人： Karthikeyan Avudaiyappan , Mohammad Abdallah
IPC分类号： G06F12/00 , G06F9/38 , G06F12/02 , G06F12/08 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3842 , G06F9/3861 , G06F12/0215 , G06F12/0862 , G06F12/0875 , G06F2212/452
摘要： Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.
摘要翻译：公开了在连接到外部互连结构的处理器中用于负载消除的系统和方法。作为在连接到外部总线的处理器中的负载消除的方法的一部分，并且响应于刷新请求以及来自加载队列的等待的推测负载的相应取消，一种或多种待处理的投机负载位于处理器外部的指令流水线中，从负载转换为预取。对应于位于处理器外部的指令流水线中的一个或多个未决投机负载的数据被访问并作为预取数据返回到高速缓存。预取数据在处理器的高速缓存位置中退出。

10. 发明申请

US20140108739A1 SYSTEMS AND METHODS FOR IMPLEMENTING WEAK STREAM SOFTEARE DATA AND INSTRUCTION PREFETCHING USING A HARDWARE DATA PREFETCHER 有权
标题翻译：实施弱流数据的系统和方法以及使用硬件数据预编译器的指令预选
公开(公告)号：US20140108739A1
公开(公告)日：2014-04-17
申请号：US13649469
申请日：2012-10-11
申请人： Karthikeyan Avudaiyappan , Mohammad Abdallah
发明人： Karthikeyan Avudaiyappan , Mohammad Abdallah
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/00 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F12/0215 , G06F2212/602 , G06F2212/6026
摘要： A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations.
摘要翻译：公开了一种使用硬件数据预取器的弱流软件数据和指令预取方法。一种方法包括：使用硬件数据预取器来确定软件是否包括软件预取指令，以及如果软件包括软件预取指令，则访问软件预取指令。使用硬件数据预取器，基于软件预取指令执行弱流软件数据和指令预取操作，无需训练操作。

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