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1. 发明申请

US20120049186A1 SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：半导体结构
公开(公告)号：US20120049186A1
公开(公告)日：2012-03-01
申请号：US12872468
申请日：2010-08-31
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F9/7084 , H01L2223/5442 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： Test structures are formed during semiconductor processing with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
摘要翻译：测试结构在半导体处理期间用单个掩模形成，该掩模的使用方式也允许形成对准标记，这些对准标记在随后的层被图案化时不会彼此干涉。随着半导体工艺的进行，测试结构可以提供对不同类型器件的性能特征的洞察。

2. 发明授权

US07830028B2 Semiconductor test structures 有权
标题翻译：半导体测试结构
公开(公告)号：US07830028B2
公开(公告)日：2010-11-09
申请号：US11772130
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L22/34 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
摘要翻译：在半导体处理期间形成不同类型的测试结构。一种类型的测试结构包括彼此对准并且由不同层形成的特征。其他类型的测试结构包括由不同于其它测试结构特征的各层形成的特征。不同类型的测试结构形成有单个掩模，其以允许形成对准标记的方式使用，其中随后的层被图案化而不会彼此干扰。不同类型的测试结构可以随着半导体工艺的进行而深入了解不同类型器件的性能特征。

3. 发明申请

US20090004880A1 MASK REUSE IN SEMICONDUCTOR PROCESSING 有权
标题翻译：半导体处理中的掩蔽重现
公开(公告)号：US20090004880A1
公开(公告)日：2009-01-01
申请号：US11772137
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L21/32
CPC分类号： H01L21/32139 , G03F1/42 , G03F7/70633 , G03F9/7076 , H01L23/544 , H01L27/101 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.
摘要翻译：在半导体处理中，掩模被重复使用以在多层中形成相同的图案。也可以使用掩模形成允许校准精度的参考标记。使用掩模的方式有利地减轻不同层中的参考标记之间的干扰。

4. 发明授权

US06627530B2 Patterning three dimensional structures 有权
公开(公告)号：US06627530B2
公开(公告)日：2003-09-30
申请号：US09746204
申请日：2000-12-22
申请人： Calvin K. Li , N. Johan Knall , Michael A. Vyvoda , James M. Cleeves , Vivek Subramanian
发明人： Calvin K. Li , N. Johan Knall , Michael A. Vyvoda , James M. Cleeves , Vivek Subramanian
IPC分类号： H01L214763
CPC分类号： H01L27/0688 , H01L21/32135 , H01L21/8221 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal line, where the two signal lines comprise similar materials. The method includes selectively patterning the second signal line material and the circuit without patterning the first signal line. One way the second signal line is patterned without patterning the first signal line is by modifying the etch chemistry. A second way the second signal line is patterned without patterning the first signal line is by including an etch stop between the first signal line and the second signal line. The invention is also directed at targeting a desired edge angle of a stacked circuit structure. In terms of patterning techniques, a desired edge angle is targeted by modifying, for example, the etch chemistry from one that is generally anisotropic to one that has a horizontal component to achieve an edge angle that is slightly re-entrant (i.e., having negative slope).

5. 发明授权

US06624011B1 Thermal processing for three dimensional circuits 有权
标题翻译：三维电路热处理
公开(公告)号：US06624011B1
公开(公告)日：2003-09-23
申请号：US09639750
申请日：2000-08-14
申请人： Vivek Subramanian , James M. Cleeves , N. Johan Knall , Calvin K. Li , Michael A. Vyvoda
发明人： Vivek Subramanian , James M. Cleeves , N. Johan Knall , Calvin K. Li , Michael A. Vyvoda
IPC分类号： H01L2100
CPC分类号： H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Postponing at least some thermal processing operations, as multiple levels of a three dimensional circuit are formed.
摘要翻译：当形成三维电路的多个级别时，推迟至少一些热处理操作。

6. 发明授权

US06770939B2 Thermal processing for three dimensional circuits 有权
标题翻译：三维电路热处理
公开(公告)号：US06770939B2
公开(公告)日：2004-08-03
申请号：US10256116
申请日：2002-09-26
申请人： Vivek Subramanian , James M. Cleeves , N. Johan Knall , Calvin K. Li , Michael A. Vyvoda
发明人： Vivek Subramanian , James M. Cleeves , N. Johan Knall , Calvin K. Li , Michael A. Vyvoda
IPC分类号： H01L2976
CPC分类号： H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.
摘要翻译：一种包括在从第一电平到第n电平的衬底上形成的n个电路电平的电路的装置，其中n大于1，并且n个电路电平中的每一个具有材料参数变化，其至少部分地由热处理操作同时应用于n个电路级中的一个以上。一种包括多个电路电平的电路的装置，所述多个电路电平中的每一个具有基本相似的材料参数。

7. 发明授权

US06649451B1 Structure and method for wafer comprising dielectric and semiconductor 失效
标题翻译：包括电介质和半导体的晶片的结构和方法
公开(公告)号：US06649451B1
公开(公告)日：2003-11-18
申请号：US09776000
申请日：2001-02-02
申请人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
发明人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
IPC分类号： H01L2182
CPC分类号： H01L21/76224 , H01L21/76819 , H01L23/5254 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.
摘要翻译：本发明的晶片包括半导体层和电介质层。图案化半导体层以形成半导体区域，并且电介质层沉积在半导体层的顶部上。执行化学机械平面化（CMP）以去除电介质层的一部分，暴露半导体区域的上表面。由于电介质被靶向沉积到半导体区域之间的空间中的半导体区域的上边缘，因此减小了使晶片上的所有半导体区域露出所需的CMP量。该技术降低了跨晶片的电介质层和半导体层的厚度的不均匀性。可以监测沉积在位于每个管芯边缘的抛光监测器焊盘上的电介质层或半导体层的厚度，以确定何时已经执行了足够的CMP来暴露每个半导体区域。

8. 发明授权

US08748859B2 Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars 有权
标题翻译：非易失性存储器阵列包括具有用于电隔离柱的二极管的共享二极管组件部分的轨道堆叠
公开(公告)号：US08748859B2
公开(公告)日：2014-06-10
申请号：US13441805
申请日：2012-04-06
申请人： Kang-Jay Hsia , Christopher J Petti , Calvin K Li
发明人： Kang-Jay Hsia , Christopher J Petti , Calvin K Li
IPC分类号： H01L29/02
CPC分类号： H01L27/1021
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。这些装置在上下导体组的交点处使用支柱结构形成。通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

9. 发明申请

US20120187361A1 Non-Volatile Memory Arrays Comprising Rail Stacks With A Shared Diode Component Portion For Diodes Of Electrically Isolated Pillars 有权
标题翻译：非易失性存储器阵列包括具有共享二极管组成部分的轨道堆叠用于电隔离柱的二极管
公开(公告)号：US20120187361A1
公开(公告)日：2012-07-26
申请号：US13441805
申请日：2012-04-06
申请人： Kang-Jay Hsia , Christopher J. Petti , Calvin K. Li
发明人： Kang-Jay Hsia , Christopher J. Petti , Calvin K. Li
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/1021
摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
摘要翻译：提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。这些装置在上下导体组的交点处使用支柱结构形成。通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

10. 发明授权

US07927990B2 Forming complimentary metal features using conformal insulator layer 有权
标题翻译：使用保形绝缘层形成互补的金属特征
公开(公告)号：US07927990B2
公开(公告)日：2011-04-19
申请号：US11771137
申请日：2007-06-29
申请人： Kang-Jay Hsia , Calvin K Li , Christopher J Petti
发明人： Kang-Jay Hsia , Calvin K Li , Christopher J Petti
IPC分类号： H01L21/20
CPC分类号： H01L21/76838 , H01L21/76834 , H01L27/1021
摘要： A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.
摘要翻译：提供了一种形成密集间隔的金属线的方法。通过蚀刻第一金属层形成第一组金属线。平坦地沉积在第一金属线上的薄介电层。第二金属沉积在薄介电层上，填充第一金属线之间的间隙。第二金属层被平坦化以形成插入在第一金属线之间的第二金属线，在基本上平坦的表面处共存薄介电层和第二金属层。在一些实施例中，平面化继续移除第一金属线的薄电介质覆盖顶部，在基本上平坦的表面处将第一金属线和由薄介电层隔开的第二金属线并入。

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