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1. 发明授权

US06460107B1 Integrated real-time performance monitoring facility 失效
标题翻译：集成实时性能监控设备
公开(公告)号：US06460107B1
公开(公告)日：2002-10-01
申请号：US09301870
申请日：1999-04-29
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Dinesh Ranganathan
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Dinesh Ranganathan
IPC分类号： G06F1314
CPC分类号： G06F11/3409 , G06F11/348 , G06F11/349 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I2O) and Peripheral Components Interconnect (PCI) specifications.
摘要翻译：集成电路（IC）数据处理器中的实时性能监控设备，用于监控与不同总线活动相关的事件。监控设备可通过总线连接IC访问。事件包括设备采集和所有权时间，以及给定总线上的请求和授权数量。这些事件由集成在IC中的多个事件计数器计入事件和持续时间。当计数器溢出时，IC可以通知软件。 IC可以具有多个时钟域，包括例如以不同时钟频率工作的多个总线接口，其中来自不同时钟域的事件可以被同一计数器跟踪。在一个实施例中，性能监视设备被集成到符合流行的智能I / O（I2O）和外围组件互连（PCI）规范的I / O处理器（IOP）芯片中。

2. 发明授权

US6003122A Direct memory access controller 失效
标题翻译：直接内存访问控制器
公开(公告)号：US6003122A
公开(公告)日：1999-12-14
申请号：US724179
申请日：1996-09-30
申请人： Mark A. Yarch , Byron R. Gillespie
发明人： Mark A. Yarch , Byron R. Gillespie
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration.A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size.A computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access (DMA) controller is also provided. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus and a DMA IDLE. The error handling logic aborts a DMA transfer when the error signal and the DMA signal are asserted and the retry signal is deasserted.
摘要翻译：提供了将数据段从第一存储设备传送到第二存储设备的对准逻辑电路。对准逻辑电路包括第一和第二对准级，以及对准控制逻辑，其控制第一和第二对准级，使得第一对准级根据第二配置输出在第一维中对齐的数据，并且第二对准级输出根据第二配置在第二维度中排列数据。提供具有DMA控制器的计算机系统，其具有存储器写入和无效逻辑电路。当DMA字节数大于或等于高速缓存行大小时，存储器写入和无效逻辑电路产生存储器写入和无效使能信号，并且当前传输加法器是高速缓存行大小的倍数。还提供了包括主机处理器，耦合到主处理器的第一总线，耦合到第二总线的第二总线，从属电路和直接存储器存取（DMA）控制器）的计算机系统。 DMA控制器包括耦合到主机处理器的DMA错误处理逻辑，用于接收指示从属电路的重试请求的重试信号。 DMA错误处理逻辑还接收指示第一总线上的错误和DMA IDLE的错误信号。当错误信号和DMA信号被断言并且重试信号被断言时，错误处理逻辑中止DMA传输。

3. 发明授权

US5761532A Direct memory access controller with interface configured to generate wait states 失效
标题翻译：具有配置为生成等待状态的接口的直接内存访问控制器
公开(公告)号：US5761532A
公开(公告)日：1998-06-02
申请号：US581163
申请日：1995-12-29
申请人： Mark A. Yarch , Byron R. Gillespie , Marc A. Goldschmidt
发明人： Mark A. Yarch , Byron R. Gillespie , Marc A. Goldschmidt
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.
摘要翻译：提供一种包括本地存储器，耦合到本地存储器的本地总线，外围总线和直接存储器存取（DMA）控制器）的计算机系统。 DMA控制器在本地总线和外设总线之间执行DMA传输数据。 DMA包括用于存储要传送的数据的DMA队列和用于确定DMA控制器的总线所有权状态的总线所有权状态电路。 DMA控制器还包括耦合到DMA队列和状态电路的本地总线接口电路，用于在DMA队列满时通过本地总线暂停数据从本地总线传送到DMA队列而不放弃DMA所有权，并且状态电路指示DMA控制器拥有外围总线和本地总线的所有权。

4. 发明授权

US5513337A System for protecting unauthorized memory accesses by comparing base memory address with mask bits and having attribute bits for identifying access operational mode and type 失效
标题翻译：用于通过将基本存储器地址与掩码位进行比较并具有用于识别访问操作模式和类型的属性位来保护未经授权的存储器访问的系统
公开(公告)号：US5513337A
公开(公告)日：1996-04-30
申请号：US249011
申请日：1994-05-25
申请人： Byron R. Gillespie , Elliot D. Garbus , Mitchell A. Kahn , Thomas M. Johnson , Dennis M. O'Connor , Jay S. Heeb
发明人： Byron R. Gillespie , Elliot D. Garbus , Mitchell A. Kahn , Thomas M. Johnson , Dennis M. O'Connor , Jay S. Heeb
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.
摘要翻译：所描述的系统和方法提供了对存储器访问的检测和保护，而不需要由存储器管理单元引起的开销。该处理器包括一个保护的存储器单元，其监视通过监视跨存储器总线的传输来执行的存储器访问。保护存储器单元包括多个寄存器，其识别可能导致存储器保护或检测违规发生的存储器地址和模式。如果发生存储器保护违规，则在完成之前发出取消信号以取消存储器操作，以保护存储器免受未经授权的访问。如果检测到存储器冲突，则允许存储器操作完成，并且向处理器发出故障信号以识别已经检测到存储器违规。由于保护机构的结构在处理器中不需要单独的周期，并且简单地监视存储器总线以进行存储器访问，所以可以在处理器没有额外的开销的情况下执行存储器保护和检测。

5. 发明授权

US06145043A Boolean and movement accelerator 失效
标题翻译：布尔运动加速器
公开(公告)号：US06145043A
公开(公告)日：2000-11-07
申请号：US92101
申请日：1998-06-05
申请人： Terence Sych , Byron R. Gillespie , Ravi S. Rao
发明人： Terence Sych , Byron R. Gillespie , Ravi S. Rao
IPC分类号： G06F9/308 , G06F9/38 , G06F11/10 , G06F13/00 , G06F7/00 , H03K19/00
CPC分类号： G06F9/30018 , G06F11/1076 , G06F9/3816 , G06F9/3879
摘要： An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.
摘要翻译：一种应用加速器（AA）单元，其在一个实施例中是I / O处理器（IOP）集成电路的一部分。 AAU包括用于提高存储应用的性能的逻辑电路，例如廉价磁盘冗余阵列（RAID）。布尔单元在多个数据块上执行诸如异或（XOR）的操作，以形成写入冗余磁盘阵列的图像奇偶校验块。 AAU与内存映射编程接口相关联，允许由IOP中的核心处理器执行的软件利用AAU来加速RAID存储应用以及使用描述符构造的本地存储器DMA类型传输。

6. 发明授权

US5657475A System for protecting memory accesses by comparing the upper and lower bounds addresses and attribute bits identifying unauthorized combinations of type of operation and mode of access 失效
标题翻译：通过比较识别操作类型和访问方式的未授权组合的上限和下限地址和属性位来保护存储器访问的系统
公开(公告)号：US5657475A
公开(公告)日：1997-08-12
申请号：US582969
申请日：1996-01-04
申请人： Byron R. Gillespie , Elliot D. Garbus , Mitchell A. Kahn , Thomas M. Johnson , Dennis M. O'Connor , Jay S. Heeb
发明人： Byron R. Gillespie , Elliot D. Garbus , Mitchell A. Kahn , Thomas M. Johnson , Dennis M. O'Connor , Jay S. Heeb
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.
摘要翻译：所描述的系统和方法提供了对存储器访问的检测和保护，而不需要由存储器管理单元引起的开销。该处理器包括一个保护的存储器单元，其监视通过监视跨存储器总线的传输来执行的存储器访问。保护存储器单元包括多个寄存器，其识别可能导致存储器保护或检测违规发生的存储器地址和模式。如果发生存储器保护违规，则在完成之前发出取消信号以取消存储器操作，以保护存储器免受未经授权的访问。如果检测到存储器冲突，则允许存储器操作完成，并且向处理器发出故障信号以识别已经检测到存储器违规。由于保护机构的结构在处理器中不需要单独的周期，并且简单地监视存储器总线以进行存储器访问，所以可以在处理器没有额外的开销的情况下执行存储器保护和检测。

7. 发明授权

US07007126B2 Accessing a primary bus messaging unit from a secondary bus through a PCI bridge 失效
标题翻译：通过PCI桥从辅助总线访问主总线消息单元
公开(公告)号：US07007126B2
公开(公告)日：2006-02-28
申请号：US09023494
申请日：1998-02-13
申请人： Byron R. Gillespie , Barry R. Davis , William Futral
发明人： Byron R. Gillespie , Barry R. Davis , William Futral
IPC分类号： G06F13/38
CPC分类号： G06F13/404 , G06F12/0284
摘要： An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (I2O®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the I2O protocol without interrupting the host processor which normally resides on the primary PCI bus.
摘要翻译：具有处理器，桥接单元和将计算机系统中的主要，次要和第三总线耦合的I / O消息单元的I / O子系统。桥单元可配置为声明从辅助总线访问消息单元（MU）地址范围的请求，MU本身耦合到主总线。当发出I / O请求时，MU中断处理器，响应处理器从MU指针读取到I / O消息，然后可以执行I / O消息。为了促进在希望访问MU的主总线或辅助总线上为代理编写的软件的可移植性，I / O子系统的主地址转换单元和辅助地址转换单元被编程为要求相同的地址转换窗口，其中MU 地址范围是主ATU地址转换窗口的一部分，并且辅助ATU被配置为不在MU地址范围内要求请求。在特定实施例中，I / O子系统可以被实现为单个集成电路芯片（I / O处理器），其被配置为支持智能I / O（I 2 O）协议与外围组件互连（PCI）主要和次要系统总线相关。通过配置桥接器要求辅助总线上的MU地址范围，I / O子系统可以允许辅助总线上的代理执行I＆lt; 2＆gt; O协议，而不中断通常驻留在主机处理器主PCI总线。

8. 发明授权

US06678777B2 Integrated real-time performance monitoring facility 失效
标题翻译：集成实时性能监控设备
公开(公告)号：US06678777B2
公开(公告)日：2004-01-13
申请号：US10254408
申请日：2002-09-25
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus
IPC分类号： G06F1314
CPC分类号： G06F11/3409 , G06F11/348 , G06F11/349 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I2O) and Peripheral Components Interconnect (PCI) specifications.
摘要翻译：集成电路（IC）数据处理器中的实时性能监控设备，用于监控与不同总线活动相关的事件。监控设备可通过总线连接IC访问。事件包括设备采集和所有权时间，以及给定总线上的请求和授权数量。这些事件由集成在IC中的多个事件计数器计入事件和持续时间。当计数器溢出时，IC可以通知软件。 IC可以具有多个时钟域，包括例如以不同时钟频率工作的多个总线接口，其中来自不同时钟域的事件可以被同一计数器跟踪。在一个实施例中，性能监视设备被集成到符合流行的智能I / O（I2O）和外围组件互连（PCI）规范的I / O处理器（IOP）芯片中。

9. 发明授权

US06070182A Data processor having integrated boolean and adder logic for accelerating storage and networking applications 失效
标题翻译：具有集成布尔和加法器逻辑的数据处理器，用于加速存储和联网应用
公开(公告)号：US06070182A
公开(公告)日：2000-05-30
申请号：US92275
申请日：1998-06-05
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Joseph Murray
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Joseph Murray
IPC分类号： G06F7/57 , G06F11/10 , G06F7/50
CPC分类号： G06F7/57 , G06F11/1076
摘要： An application accelerator unit (AAU) that is integrated as part of a data processor, such as an I/O processor (IOP) integrated circuit. In one embodiment, the AAU includes logic for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). The AAU performs boolean operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is then written to the redundant disk array. Additionally, the AAU may feature adder logic configured to perform an addition such as a network header checksum calculation on each data packet. The AAU includes a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating storage and networking applications as well as for local memory DMA-type transfers, using the chain descriptor construct.
摘要翻译：作为诸如I / O处理器（IOP）集成电路的数据处理器的一部分集成的应用加速器单元（AAU）。在一个实施例中，AAU包括用于改善诸如廉价磁盘冗余阵列（RAID）的存储应用的性能的逻辑。 AAU在多个数据块上执行布尔运算（例如异或（XOR））以形成图像奇偶校验块，然后将其写入冗余磁盘阵列。此外，AAU可以具有加法器逻辑，其被配置为对每个数据分组执行诸如网络报头校验和计算的相加。 AAU包括内存映射编程接口，允许IOP中的核心处理器执行的软件利用AAU来加速存储和联网应用以及使用链描述符构造的本地存储器DMA类型传输。

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