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1. 发明授权

US09472659B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09472659B2
公开(公告)日：2016-10-18
申请号：US14813848
申请日：2015-07-30
申请人： Jin-Hyun Noh , Su-Tae Kim , Jae-Hyun Yoo , Byeong-Ryeol Lee , Jong-Sung Jeon
发明人： Jin-Hyun Noh , Su-Tae Kim , Jae-Hyun Yoo , Byeong-Ryeol Lee , Jong-Sung Jeon
IPC分类号： H01L29/78 , H01L29/161 , H01L27/088 , H01L21/00
CPC分类号： H01L29/063 , H01L27/0886 , H01L27/092 , H01L27/0922 , H01L29/0619 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0865 , H01L29/0882 , H01L29/1054 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/408 , H01L29/4238 , H01L29/66545 , H01L29/66659 , H01L29/7816 , H01L29/7835 , H01L29/785 , H01L29/7851
摘要： Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.
摘要翻译：半导体器件包括在衬底上的沟道层，沟道层包括具有不同于衬底的晶格常数的晶格常数的材料，沟道层上的第一栅电极，第一导电类型的第一源极区在所述第一源极区域的第一导电类型的第一主体区域和与所述第一源极区域接触的第一导电类型的第一体区域，设置在所述第一栅极电极的第二侧的所述第一导电类型的第一漏极区域，在第一漏区下面的第一导电类型的漂移区，并与第一漏极区以及沟道层和第一漂移区中的第一柱状区域接触。第一螺柱区域的杂质浓度高于第一漂移区域的杂质浓度。

2. 发明申请

US20070077715A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070077715A1
公开(公告)日：2007-04-05
申请号：US11541569
申请日：2006-10-03
申请人： Tae-Woong Kang , Byeong-Ryeol Lee , Sung-Man Hwang
发明人： Tae-Woong Kang , Byeong-Ryeol Lee , Sung-Man Hwang
IPC分类号： H01L21/336
CPC分类号： H01L21/823456 , H01L21/823437 , H01L21/82345 , H01L21/823462 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621
摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. A dummy pattern may be formed on a semiconductor substrate. Source and drain regions may be formed on the semiconductor substrate at sides of the dummy pattern. A first metal silicide layer may be formed on the source and drain regions. A recess region may be formed in the semiconductor substrate under the dummy pattern. A gate insulating layer and a gate electrode may be formed in the recess region.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。可以在半导体衬底上形成虚设图案。源极和漏极区域可以在虚设图案的侧面的半导体衬底上形成。可以在源区和漏区上形成第一金属硅化物层。可以在虚设图案下的半导体衬底中形成凹陷区域。栅极绝缘层和栅电极可以形成在凹陷区域中。

3. 发明授权

US07067360B2 Method of fabricating a fin field effect transistor 失效
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US07067360B2
公开(公告)日：2006-06-27
申请号：US11024518
申请日：2004-12-28
申请人： Byeong Ryeol Lee
发明人： Byeong Ryeol Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795
摘要： A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a sidewall damaged by the etching remove a sacrificial silicon oxide layer. The example method also deposits a high-K dielectric as a gate dielectric, deposits a metal layer, planarizes the metal layer to a height of a hard oxide, forms a nitride layer on the planarized metal layer, and patterns the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern. Additionally, the example method forms a metal gate using the nitride layer pattern, removes a remaining hard oxide mask, and grows a sidewall oxide layer on the metal gate.
摘要翻译：公开了制造鳍式场效应晶体管的方法。示例性方法形成热氧化层作为用于在SOI衬底上蚀刻硅鳍片的硬掩模，转印翅片图案，通过使用鳍状图案作为蚀刻掩模进行蚀刻形成鳍状FET体，并且还原由蚀刻去除牺牲氧化硅层。该示例方法还沉积高K电介质作为栅极电介质，沉积金属层，将金属层平坦化为硬氧化物的高度，在平坦化的金属层上形成氮化物层，并使用硬的用于形成图案以形成氮化物层图案的掩模。此外，示例性方法使用氮化物层图案形成金属栅极，去除剩余的硬氧化物掩模，并在金属栅极上生长侧壁氧化物层。

4. 发明授权

US07074711B2 Method of fabricating a test pattern for junction leakage current 失效
标题翻译：制造结漏电流测试图形的方法
公开(公告)号：US07074711B2
公开(公告)日：2006-07-11
申请号：US11027349
申请日：2004-12-29
申请人： Byeong Ryeol Lee
发明人： Byeong Ryeol Lee
IPC分类号： H01L21/4763
CPC分类号： H01L22/34 , H01L21/28518
摘要： A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.
摘要翻译：公开了一种形成用于测量结漏电流的自对准硅化物图案的方法。示例性方法在硅衬底上形成器件隔离结构，在器件隔离结构之间形成阱区，在阱区上形成源区和漏区，并在源区和漏区上形成自对准硅化物层。该示例性方法还去除了一部分自对准硅化物层，在硅化物层上沉积了层间介质层，并在层间电介质层中形成通孔，并将金属填充到通孔中以形成通孔。该示例性方法进一步使层间电介质层和通孔平坦化，并在层间电介质层上形成金属互连。

5. 发明授权

US07229870B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07229870B2
公开(公告)日：2007-06-12
申请号：US11027513
申请日：2004-12-29
申请人： Byeong Ryeol Lee
发明人： Byeong Ryeol Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.
摘要翻译：公开了制造CMOS晶体管的方法。所公开的方法包括分别在第一和第二井上形成第一和第二栅极图案; 在所述衬底上形成侧壁绝缘层; 通过NMOS LDD离子注入在第一阱中形成第一轻掺杂区; 在所述衬底上形成第一栅极间隔绝缘层; 通过PMOS LDD离子注入在第二阱中形成第二轻掺杂区; 在第一栅极间隔绝缘层上依次层叠间隔绝缘层和第二栅极间隔绝缘层; 在所述第一和第二栅极图案的侧壁上形成第一和第二间隔物; 以及分别通过NMOS和PMOS源/漏离子注入在第一阱和第二阱中形成第一和第二重掺杂区。

6. 发明授权

US07179713B2 Method of fabricating a fin transistor 失效
标题翻译：制造鳍式晶体管的方法
公开(公告)号：US07179713B2
公开(公告)日：2007-02-20
申请号：US11025244
申请日：2004-12-28
申请人： Byeong Ryeol Lee
发明人： Byeong Ryeol Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of fabricating a fin transistor is disclosed. An example method stacks a mask oxide layer and a nitride layer on a semiconductor substrate, forms a fin by etching the nitride and mask oxide layers and silicon, forms an insulating oxide layer, and forms a gate electrode by etching the insulating oxide layer corresponding to a gate forming area using a gate mask, by forming a gate oxide layer on a sidewall of the silicon exposed by the etch and burying a metal. The example method also removes the remaining insulating oxide layer using an etch rate difference, forms a gate spacer, and forms source/drain regions in the silicon substrate to be aligned with the gate electrode. Additionally, the example method forms a second insulating oxide layer over the substrate, etches the second insulating oxide layer using a metal mask, forms contact holes on the source/drain regions, respectively, and fills the contact holes and the portion etched via the metal mask with a metal.
摘要翻译：公开了一种制造鳍式晶体管的方法。示例性方法在半导体衬底上堆叠掩模氧化物层和氮化物层，通过蚀刻氮化物并掩蔽氧化物层和硅来形成鳍，形成绝缘氧化物层，并通过蚀刻对应于使用栅极掩模的栅极形成区域，通过在通过蚀刻暴露的硅的侧壁上形成栅极氧化物层并且埋入金属。示例性方法还使用蚀刻速率差去除剩余的绝缘氧化物层，形成栅极间隔物，并在硅衬底中形成与栅电极对准的源/漏区。此外，示例性方法在衬底上形成第二绝缘氧化物层，使用金属掩模蚀刻第二绝缘氧化物层，分别在源/漏区上形成接触孔，并填充接触孔和通过金属蚀刻的部分面具与金属。

7. 发明申请

US20160141413A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20160141413A1
公开(公告)日：2016-05-19
申请号：US14813848
申请日：2015-07-30
申请人： Jin-Hyun NOH , Su-Tae KIM , Jae-Hyun YOO , Byeong-Ryeol LEE , Jong-Sung JEON
发明人： Jin-Hyun NOH , Su-Tae KIM , Jae-Hyun YOO , Byeong-Ryeol LEE , Jong-Sung JEON
IPC分类号： H01L29/78 , H01L27/088 , H01L29/161
CPC分类号： H01L29/063 , H01L27/0886 , H01L27/092 , H01L27/0922 , H01L29/0619 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0865 , H01L29/0882 , H01L29/1054 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/408 , H01L29/4238 , H01L29/66545 , H01L29/66659 , H01L29/7816 , H01L29/7835 , H01L29/785 , H01L29/7851
摘要： Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.
摘要翻译：半导体器件包括在衬底上的沟道层，沟道层包括具有不同于衬底的晶格常数的晶格常数的材料，沟道层上的第一栅电极，第一导电类型的第一源极区在所述第一源极区域的第一导电类型的第一主体区域和与所述第一源极区域接触的第一导电类型的第一主体区域，设置在所述第一栅极电极的第二侧的所述第一导电类型的第一漏极区域，在第一漏区下面的第一导电类型的漂移区，并与第一漏极区以及沟道层和第一漂移区中的第一柱状区域接触。第一螺柱区域的杂质浓度高于第一漂移区域的杂质浓度。

8. 发明授权

US6066523A Method for fabricating a semiconductor device having triple wells 失效
标题翻译：制造具有三孔的半导体器件的方法
公开(公告)号：US6066523A
公开(公告)日：2000-05-23
申请号：US105304
申请日：1998-06-26
申请人： Dae Yong Shim , Byeong Ryeol Lee
发明人： Dae Yong Shim , Byeong Ryeol Lee
IPC分类号： H01L21/266 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/266
摘要： The present invention relates to a method for fabricating semiconductor devices having triple wells, the present invention has an effect as follows. The present invention provides carrying out N-well and P-well and R-well ion implantation using a mask for implanting two wells after forming an element isolation oxide film, defining an accurate well region by forming wells having an accurate profile due to activating impurity ions in accordance with the thermal process, and improving the punch characteristic between a well and a well.
摘要翻译：本发明涉及一种制造具有三阱的半导体器件的方法，本发明具有如下效果。本发明提供了使用掩模进行N阱和P阱和R阱离子注入，所述掩模用于在形成元件隔离氧化物膜之后注入两个阱，通过由于活化杂质形成具有精确分布的阱来限定精确的阱区离子，并提高井与井之间的冲击特性。

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