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1. 发明授权

US07492654B2 Memory device for retaining data during power-down mode and method of operating the same 有权
标题翻译：用于在掉电模式下保留数据的存储器件及其操作方法
公开(公告)号：US07492654B2
公开(公告)日：2009-02-17
申请号：US11423673
申请日：2006-06-12
申请人： Myung-Gyoo Won , Bu-Il Jung
发明人： Myung-Gyoo Won , Bu-Il Jung
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C7/065 , G11C11/4091 , G11C2207/065
摘要： A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.
摘要翻译：存储器件包括位线读出放大器，配置为产生指示存储器件工作模式的内部控制信号的命令解码器，以及位线读出放大器控制器，被配置为选择性地将外部电压作为电源电压施加到位线路感测放大器响应内部控制信号。

2. 发明授权

US08874996B2 Memory device having reconfigurable refresh timing 有权
标题翻译：具有可重新配置的刷新时序的存储器件
公开(公告)号：US08874996B2
公开(公告)日：2014-10-28
申请号：US13597416
申请日：2012-08-29
申请人： Bu-Il Jung
发明人： Bu-Il Jung
IPC分类号： G11C29/00 , G06F11/10 , H03M13/29 , G11C11/00
CPC分类号： G06F11/1048 , G11C11/00 , G11C11/406 , G11C2029/0411 , G11C2211/4061 , G11C2211/4062 , H03M13/29
摘要： A memory device comprises a normal storage area comprising first and second subsets configured to store first and second normal data, respectively, an error code storage area configured to store first and second error codes corresponding to the first and second normal data, an error detector configured to receive the first and second normal data and the first and second error codes, and further configured to detect the presence or absence of one or more errors in the first and second normal data or the first and second error codes, and a refresh controller configured to set respective refresh cycle times of the first and second subsets to different values according to the presence or absence of one or more errors in the first and second normal data or error codes.
摘要翻译：存储装置包括：正常存储区域，包括分别存储第一和第二正常数据的第一和第二子集;错误代码存储区域，被配置为存储对应于第一和第二正常数据的第一和第二错误代码;配置的错误检测器接收第一和第二正常数据以及第一和第二错误代码，并且还被配置为检测第一和第二正常数据或第一和第二错误代码中是否存在一个或多个错误，并且配置有刷新控制器根据第一和第二正常数据或错误代码中存在或不存在一个或多个错误，将第一和第二子集的各个刷新循环时间设置为不同的值。

3. 发明申请

US20130304982A1 MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHODS THEREOF 有权
标题翻译：存储器件，存储器系统及其操作方法
公开(公告)号：US20130304982A1
公开(公告)日：2013-11-14
申请号：US13836659
申请日：2013-03-15
申请人： Bu Il JUNG , So Young KIM
发明人： Bu Il JUNG , So Young KIM
IPC分类号： G11C11/403
CPC分类号： G11C11/403 , G11C11/40615 , G11C11/40622
摘要： A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.
摘要翻译：提供了存储器件，存储器系统及其操作方法。包括与第一存储单元相邻的第一存储器单元和第二存储单元的存储器件的操作方法包括：在每次访问第一存储器单元时对第二存储器单元的干扰值进行计数，更新第二存储单元的扰动计数值所述第二存储单元基于所述计数，基于所述第二存储单元的干扰计数值，期望阈值和最大扰动计数值来调整刷新调度，以及重置所述第二存储单元的扰动计数值和所述最大扰动根据调整后的刷新时间表刷新第二存储单元时的计数值。

4. 发明申请

US20060170478A1 Delay circuit for semiconductor device 审中-公开
标题翻译：半导体器件延迟电路
公开(公告)号：US20060170478A1
公开(公告)日：2006-08-03
申请号：US11344844
申请日：2006-02-01
申请人： Bu-Il Jung
发明人： Bu-Il Jung
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A delay circuit for a semiconductor device includes a variable resistor unit having a resistance value adjusted in response to a control signal, and a variable load unit having a capacitance value adjusted in response to the control signal. The delay circuit of the present invention includes a variable resistor unit having a variable resistance value and a variable load unit having a variable capacitance value. The delay circuit for a semiconductor device can precisely adjust the delay time of a signal. Further, the capacitance of the variable load unit is very low in an operation mode in which the delay circuit of the present invention is controlled so that it has a short delay time. Therefore, the delay time can be adjusted to a short time by the delay circuit of the present invention.
摘要翻译：半导体器件的延迟电路包括具有响应于控制信号调整的电阻值的可变电阻器单元和具有响应于控制信号调整的电容值的可变负载单元。本发明的延迟电路包括具有可变电阻值的可变电阻器单元和具有可变电容值的可变负载单元。半导体器件的延迟电路可以精确地调整信号的延迟时间。此外，在本发明的延迟电路被控制为具有短的延迟时间的操作模式中，可变负载单元的电容非常低。因此，可以通过本发明的延迟电路将延迟时间调整到短时间。

5. 发明授权

US09257169B2 Memory device, memory system, and operating methods thereof 有权
标题翻译：存储器件，存储器系统及其操作方法
公开(公告)号：US09257169B2
公开(公告)日：2016-02-09
申请号：US13836659
申请日：2013-03-15
申请人： Bu Il Jung , So Young Kim
发明人： Bu Il Jung , So Young Kim
IPC分类号： G11C11/40 , G11C11/403 , G11C11/406
CPC分类号： G11C11/403 , G11C11/40615 , G11C11/40622
摘要： A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.
摘要翻译：提供了存储器件，存储器系统及其操作方法。包括与第一存储单元相邻的第一存储器单元和第二存储单元的存储器件的操作方法包括：在每次访问第一存储器单元时对第二存储器单元的干扰值进行计数，更新第二存储单元的扰动计数值所述第二存储单元基于所述计数，基于所述第二存储单元的干扰计数值，期望阈值和最大扰动计数值来调整刷新调度，以及重置所述第二存储单元的扰动计数值和所述最大扰动根据调整后的刷新时间表刷新第二存储单元时的计数值。

6. 发明申请

US20140029367A1 REFRESH ADDRESS GENERATOR, VOLATILE MEMORY DEVICE INCLUDING THE SAME AND METHOD OF REFRESHING THE VOLATILE MEMORY DEVICE 有权
标题翻译：刷新地址发生器，包括其的易失性存储器件以及刷新易失性存储器件的方法
公开(公告)号：US20140029367A1
公开(公告)日：2014-01-30
申请号：US13831162
申请日：2013-03-14
申请人： Bu-Il JUNG , So-Young KIM
发明人： Bu-Il JUNG , So-Young KIM
IPC分类号： G11C11/406 , G11C11/4063
CPC分类号： G11C11/40615 , G11C11/40611 , G11C11/40618 , G11C11/40626 , G11C11/4063 , G11C29/50016
摘要： A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.
摘要翻译：刷新地址生成器包括刷新序列缓冲器和刷新地址生成单元。刷新序列缓冲器存储存储器组的序列，每个存储器组包括多个存储器单元行。刷新地址生成单元响应于刷新信号，根据存储在刷新序列缓冲器中的存储器组的顺序生成多个刷新行地址。

7. 发明授权

US07586360B2 Power supply apparatus and method 有权
标题翻译：电源装置及方法
公开(公告)号：US07586360B2
公开(公告)日：2009-09-08
申请号：US11708353
申请日：2007-02-21
申请人： Bu-Il Jung
发明人： Bu-Il Jung
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/36
摘要： The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.
摘要翻译：该装置可以包括被配置为从电源电压产生电源电压和/或被配置为输出电源电压的非泵浦电源单元。该装置可以包括泵送电源单元和/或控制电路。泵送电源单元可以被配置为基于电源电压产生泵电压和/或被配置为输出泵电压。在电源电压达到第一目标电压电平之后，控制电路可以用泵电压升高电源电压。

8. 发明申请

US20070200612A1 Power supply apparatus and method 有权
标题翻译：电源装置及方法
公开(公告)号：US20070200612A1
公开(公告)日：2007-08-30
申请号：US11708353
申请日：2007-02-21
申请人： Bu-Il Jung
发明人： Bu-Il Jung
IPC分类号： H03K17/00
CPC分类号： H02M3/07 , H02M1/36
摘要： The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.
摘要翻译：该装置可以包括被配置为从电源电压产生电源电压和/或被配置为输出电源电压的非泵浦电源单元。该装置可以包括泵送电源单元和/或控制电路。泵送电源单元可以被配置为基于电源电压产生泵电压和/或被配置为输出泵电压。在电源电压达到第一目标电压电平之后，控制电路可以用泵电压升高电源电压。

9. 发明申请

US20060291311A1 MEMORY DEVICE FOR RETAINING DATA DURING POWER-DOWN MODE AND METHOD OF OPERATING THE SAME 有权
标题翻译：用于在掉电模式期间保留数据的存储器件及其操作方法
公开(公告)号：US20060291311A1
公开(公告)日：2006-12-28
申请号：US11423673
申请日：2006-06-12
申请人： Myung-Gyoo Won , Bu-Il Jung
发明人： Myung-Gyoo Won , Bu-Il Jung
IPC分类号： G11C8/00 , G11C7/02
CPC分类号： G11C5/14 , G11C7/065 , G11C11/4091 , G11C2207/065
摘要： A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.
摘要翻译：存储器件包括位线读出放大器，配置为产生指示存储器件工作模式的内部控制信号的命令解码器，以及位线读出放大器控制器，被配置为选择性地将外部电压作为电源电压施加到位线路感测放大器响应内部控制信号。

10. 发明申请

US20160048425A1 MEMORY DEVICE HAVING A SHAREABLE ERROR CORRECTION CODE CELL ARRAY 有权
标题翻译：具有可分类错误修正代码单元阵列的存储器件
公开(公告)号：US20160048425A1
公开(公告)日：2016-02-18
申请号：US14722823
申请日：2015-05-27
申请人： Hyun-joong Kim , Soo-hyeong Kim , Sang-hoon Shin , Ju-yun Jung , Ho-young Song , Kyo-min Sohn , Hae-suk Lee , Bu-il Jung , Han-vit Jeong
发明人： Hyun-joong Kim , Soo-hyeong Kim , Sang-hoon Shin , Ju-yun Jung , Ho-young Song , Kyo-min Sohn , Hae-suk Lee , Bu-il Jung , Han-vit Jeong
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G11C29/52 , G06F11/1048 , G11C2029/0411
摘要： A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.
摘要翻译：一种存储器件，包括：纠错码（ECC）单元阵列; ECC引擎，被配置为接收要写入存储单元阵列的写入数据，并为写入数据生成内部奇偶校验位; 以及ECC选择单元，被配置为接收内部奇偶校验位和外部奇偶校验位，并且响应于控制信号的第一电平将内部奇偶校验位存储在ECC单元阵列中，并且响应于第二级别的控制信号存储ECC单元阵列中的外部奇偶校验位。

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