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    • 1. 发明授权
    • Method of forming a pattern and method of manufacturing a capacitor using the same
    • 形成图案的方法和使用其形成电容器的方法
    • US07638388B2
    • 2009-12-29
    • US11945922
    • 2007-11-27
    • Kyoung-Min KimJae-Ho KimYoung-Ho KimBoo-Deuk KimSeok Han
    • Kyoung-Min KimJae-Ho KimYoung-Ho KimBoo-Deuk KimSeok Han
    • H01L21/8244
    • H01G4/33H01G4/40H01L27/10817H01L27/10852H01L28/91
    • In a method of forming a pattern and a method of manufacturing a capacitor using the same, a conductive layer is formed on a mold layer having an opening. A first buffer layer pattern including a polymer having a repeating unit of anthracene-methyl methacrylate and a repeating unit of alkoxyl-vinyl benzene is formed on the conductive layer in the opening. The first buffer layer pattern is baked to cross-link the polymers and form a second buffer layer pattern that is insoluble in a developing solution. The conductive layer on a top portion of the mold layer is selectively removed by using the second buffer layer pattern as an etching mask. Accordingly, a conductive pattern for a semiconductor device is formed. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.
    • 在形成图案的方法和使用其的电容器的制造方法中,在具有开口的模具层上形成导电层。 在开口中的导电层上形成包含具有蒽 - 甲基丙烯酸甲酯的重复单元的聚合物和烷氧基 - 乙烯基苯的重复单元的第一缓冲层图案。 烘烤第一缓冲层图案以交联聚合物并形成不溶于显影溶液的第二缓冲层图案。 通过使用第二缓冲层图案作为蚀刻掩模,选择性地去除模层顶部的导电层。 因此,形成用于半导体器件的导电图案。 形成图案的方法可以简化电容器和半导体器件的制造工艺,并且可以提高它们的效率。