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1. 发明授权

US09323427B2 Method and apparatus for displaying lists 有权
标题翻译：用于显示列表的方法和装置
公开(公告)号：US09323427B2
公开(公告)日：2016-04-26
申请号：US13270337
申请日：2011-10-11
申请人： Seock Hyun Yu , Giang Yoon Kwon , Chang Mo Yang , Jae Myung Lee , Yu Sic Kim , Bo Young Lee , Eun Ju Lee
发明人： Seock Hyun Yu , Giang Yoon Kwon , Chang Mo Yang , Jae Myung Lee , Yu Sic Kim , Bo Young Lee , Eun Ju Lee
IPC分类号： G06F3/0483 , G06F3/0482
CPC分类号： G06F3/0483 , G06F3/0482 , G06F3/0485 , G06F2203/04803
摘要： A list display method and apparatus are disclosed. The list display method, for a terminal having a display unit, includes detecting a necessity for displaying a list, classifying list items into viewable items and aggregated items, displaying the viewable items in the list view region and displaying information regarding the aggregated items in the list aggregate region. Responsive to inputs aggregate items may be classified as viewable items and corresponding ones of the viewable items are classified as aggregate items.
摘要翻译：公开了列表显示方法和装置。列表显示方法，对于具有显示单元的终端，包括检测列表的显示必要性，将列表项分类为可查看项目和聚合项目，将可查看项目显示在列表视图区域中，并且显示有关聚合项目的信息列表聚合区域。响应输入的总项可以分类为可查看项目，相应的可查看项目被分类为总项目。

2. 发明申请

US20150060988A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150060988A1
公开(公告)日：2015-03-05
申请号：US14519821
申请日：2014-10-21
申请人： Bo-Young LEE , Jongwan CHOI , Myoungbum LEE
发明人： Bo-Young LEE , Jongwan CHOI , Myoungbum LEE
IPC分类号： H01L27/115 , H01L23/532 , H01L23/528
CPC分类号： H01L27/11582 , H01L21/76229 , H01L21/764 , H01L23/528 , H01L23/5329 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.
摘要翻译：半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

3. 发明授权

US08492223B2 Methods of manufacturing flash memory devices by selective removal of nitrogen atoms 有权
标题翻译：通过选择性去除氮原子来制造闪存器件的方法
公开(公告)号：US08492223B2
公开(公告)日：2013-07-23
申请号：US13085631
申请日：2011-04-13
申请人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
发明人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
IPC分类号： H01L21/321
CPC分类号： H01L21/3105 , H01L21/76826 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.
摘要翻译：制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

4. 发明申请

US20100230741A1 SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC 审中-公开
标题翻译：具有气隙隔离绝缘电介质的半导体器件
公开(公告)号：US20100230741A1
公开(公告)日：2010-09-16
申请号：US12711033
申请日：2010-02-23
申请人： Jongwan Choi , Eunkee Hong , Bo-Young Lee , Tae-Jong Han , Juseon Goo , Kyungmun Byun
发明人： Jongwan Choi , Eunkee Hong , Bo-Young Lee , Tae-Jong Han , Juseon Goo , Kyungmun Byun
IPC分类号： H01L29/792 , H01L29/06
CPC分类号： H01L29/7881 , H01L21/76229 , H01L21/764 , H01L27/11521 , H01L27/11531 , H01L27/11568 , H01L29/0649
摘要： A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region.
摘要翻译：隧道绝缘层和电荷存储层依次层叠在基板上。凹陷区域穿透电荷存储层，隧道绝缘层和基底的一部分。凹陷区域由底表面和从底表面延伸的侧表面限定。第一电介质图案包括覆盖底面的底部和从底部延伸并覆盖凹部区域的侧表面的一部分的内壁。第二电介质图案位于第一电介质图案的内壁之间的凹陷区域中，并且第二电介质图案包围气隙。由第二电介质图案包围的空气间隙可以沿着远离凹部区域的底表面的方向延伸穿过第二电介质图案的主要部分。

5. 发明申请

US20100167490A1 Method of Fabricating Flash Memory Device 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US20100167490A1
公开(公告)日：2010-07-01
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

6. 发明申请

US20100109211A1 APPARATUS FOR FORMING LONGITUDINAL THERMAL-FATIGUE CRACKS 失效
标题翻译：形成长期热疲劳裂纹的装置
公开(公告)号：US20100109211A1
公开(公告)日：2010-05-06
申请号：US12325726
申请日：2008-12-01
申请人： Bo Young LEE , Jae Seong KIM , Woong Ki HWANG
发明人： Bo Young LEE , Jae Seong KIM , Woong Ki HWANG
IPC分类号： C21D1/78
CPC分类号： G01N3/60 , G01N2203/0062
摘要： An apparatus for forming longitudinal thermal fatigue cracks. A heating unit has an induction coil disposed adjacent to an outer circumference of one side of a tubular test piece, on an inner surface of which a notch is formed. A cooling unit has a cooling water pump and a cooling water hose which forcibly injects cooling water from a cooling water storage source into an inner circumference of the tubular test piece. A control unit controls operation of the heating and cooling units. A cooling block partially encloses the outer circumference of the tubular test piece so as to control a magnitude of y-axial stress, is supplied with a cooling source of fluid or gas from an outside so as to repetitively cool the tubular test piece heated by the heating unit to adjust a temperature gradient, and has a longitudinal slit for controlling crack positions.
摘要翻译：一种用于形成纵向热疲劳裂纹的装置。加热单元具有与管状试验片的一侧的外周相邻配置的感应线圈，其内表面形成有切口。冷却单元具有冷却水泵和冷却水软管，其将冷却水从冷却水存储源强制地注入到管状试验片的内周。控制单元控制加热和冷却单元的操作。冷却块部分地包围管状试件的外周，以便控制y轴向应力的大小，从外部向流体或气体供给冷却源，以便重复地冷却由加热单元来调节温度梯度，并且具有用于控制裂纹位置的纵向狭缝。

7. 发明申请

US20100091930A1 APPARATUS FOR FORMING STRESS CORROSION CRACKS 有权
标题翻译：形成应力腐蚀裂缝的装置
公开(公告)号：US20100091930A1
公开(公告)日：2010-04-15
申请号：US12325877
申请日：2008-12-01
申请人： Bo Young LEE , Jae Seong KIM , Woong Ki HWANG
发明人： Bo Young LEE , Jae Seong KIM , Woong Ki HWANG
IPC分类号： G21C9/00
CPC分类号： G01N17/00 , G21C17/00
摘要： An apparatus for forming stress corrosion cracks comprises a heating unit which includes a conductive member and a heating coil disposed adjacent to the conductive member to generate steam pressure in the tube specimen, an end holding unit, and a control unit for controlling the heating unit and the end holding unit. The stress corrosion cracks occurring in the equipment of nuclear power plants or apparatus industries during operation can be directly formed in a tube specimen using steam pressure under conditions similar to those of the actual environment of nuclear power plants, thus increasing accuracy for analysis of properties of stress corrosion cracks which are in actuality generated, thereby improving reliability of nuclear power plants or apparatus industries and effectively assuring nondestructive testing capability, resulting in very useful industrial applicability.
摘要翻译：用于形成应力腐蚀裂纹的装置包括加热单元，其包括导电构件和邻近导电构件设置的加热线圈，以在管样本中产生蒸汽压力，端部保持单元和用于控制加热单元的控制单元，末端保持单元。核电站或设备工业设备在运行过程中产生的应力腐蚀裂纹，可以直接在管状试样上形成，在与核电厂实际环境条件相似的条件下，采用蒸汽压力，从而提高分析性能的准确性实际产生的应力腐蚀裂纹，从而提高核电厂或设备行业的可靠性，有效保证无损检测能力，从而产生非常有用的工业应用。

8. 发明申请

US20070295099A1 APPARATUS FOR FORMING THERMAL FATIGUE CRACKS 失效
标题翻译：形成热疲劳裂纹的装置
公开(公告)号：US20070295099A1
公开(公告)日：2007-12-27
申请号：US11625706
申请日：2007-01-22
申请人： Bo-Young LEE , Duck Hee Ryu , Jae Seong Kim , Yong Kim , Dae Hwan An
发明人： Bo-Young LEE , Duck Hee Ryu , Jae Seong Kim , Yong Kim , Dae Hwan An
IPC分类号： G01N3/32
CPC分类号： G01N3/60 , G01N2203/0066 , G01N2203/0073 , G01N2203/027
摘要： Disclosed is an apparatus and method for forming thermal fatigue cracks in a test piece for performance demonstration of nondestructive testing. The apparatus for forming thermal fatigue cracks includes a heating unit, having a conductive member attached around the outer surface of a pipe test piece and an induction heating coil disposed adjacent to the conductive member; a cooling unit, having a cooling water pump for forcibly supplying cooling water to the inner surface of the pipe test piece from a cooling water storage source and a cooling water hose; and a control unit for controlling operation of the heating unit and the cooling unit. Accordingly, thermal fatigue cracks similar to actual thermal fatigue cracks occurring during the operation of nuclear power plants or processing industry equipment are formed in a test piece, thereby assuring effective performance demonstration of nondestructive testing.
摘要翻译：公开了一种用于在无损检测的性能演示中形成试验片中的热疲劳裂纹的装置和方法。用于形成热疲劳裂纹的装置包括加热单元，其具有附接在管道试件的外表面上的导电构件和邻近导电构件设置的感应加热线圈; 冷却单元，具有冷却水泵，用于从冷却水存储源和冷却水软管向管道试件的内表面强制供给冷却水; 以及用于控制加热单元和冷却单元的操作的控制单元。因此，在试验片中形成类似于在核电厂或加工工业设备运行期间发生的实际热疲劳裂纹的热疲劳裂纹，从而确保了非破坏性试验的有效性能演示。

9. 发明授权

US09040378B2 Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods 有权
标题翻译：形成半导体器件的方法包括使用这种方法形成的垂直沟道和半导体器件
公开(公告)号：US09040378B2
公开(公告)日：2015-05-26
申请号：US14309018
申请日：2014-06-19
申请人： Bo-Young Lee , Jong-Wan Choi , Dae-Hun Choi , Myoung-Bum Lee
发明人： Bo-Young Lee , Jong-Wan Choi , Dae-Hun Choi , Myoung-Bum Lee
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28 , H01L21/02
CPC分类号： H01L27/11556 , H01L21/02488 , H01L21/02532 , H01L21/02595 , H01L21/28273 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/7827
摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
摘要翻译：提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。孔可以暴露多个绝缘图案和多个导电图案的侧壁。多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上垂直于衬底的上表面。

10. 外观设计

USD718317S1 Display screen with graphical user interface 有权
公开(公告)号：USD718317S1
公开(公告)日：2014-11-25
申请号：US29422918
申请日：2012-05-25
申请人： Chang-Mo Yang , Kyung-Dae Park , Bo-Young Lee , Hye-Bin Park
设计人： Chang-Mo Yang , Kyung-Dae Park , Bo-Young Lee , Hye-Bin Park

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