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1. 发明申请

US20110256708A1 Methods of Manufacturing Flash Memory Devices by Selective Removal of Nitrogen Atoms 有权
标题翻译：通过选择性去除氮原子制造闪存器件的方法
公开(公告)号：US20110256708A1
公开(公告)日：2011-10-20
申请号：US13085631
申请日：2011-04-13
申请人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
发明人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
IPC分类号： H01L21/321 , H01L21/283
CPC分类号： H01L21/3105 , H01L21/76826 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.
摘要翻译：制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

2. 发明授权

US08492223B2 Methods of manufacturing flash memory devices by selective removal of nitrogen atoms 有权
标题翻译：通过选择性去除氮原子来制造闪存器件的方法
公开(公告)号：US08492223B2
公开(公告)日：2013-07-23
申请号：US13085631
申请日：2011-04-13
申请人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
发明人： Jong-wan Choi , Wan-sik Hwang , Gil-heyun Choi , Eunkee Hong , Ju-seon Goo , Bo-young Lee
IPC分类号： H01L21/321
CPC分类号： H01L21/3105 , H01L21/76826 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.
摘要翻译：制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

3. 发明授权

US08697583B2 Oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices 有权
标题翻译：氧化促进组合物，形成氧化物层的方法，以及制造半导体器件的方法
公开(公告)号：US08697583B2
公开(公告)日：2014-04-15
申请号：US13224737
申请日：2011-09-02
申请人： Kyung-seok Oh , Kyung-mun Byun , Shin-hye Kim , Deok-young Jung , Gil-heyun Choi , Eunkee Hong
发明人： Kyung-seok Oh , Kyung-mun Byun , Shin-hye Kim , Deok-young Jung , Gil-heyun Choi , Eunkee Hong
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02326 , H01L21/76224
摘要： Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
摘要翻译：根据本发明的实施方案提供的是氧化促进组合物，形成氧化物层的方法和制造半导体器件的方法。在本发明的一些实施方案中，氧化促进组合物包括具有AML结构的氧化促进剂，其中L是化学吸附在硅表面，氧化硅，氮化硅或金属上的官能团，A是一种可热分解的氧化官能团，M是允许A和L彼此共价结合的部分。

4. 发明申请

US20120058647A1 OXIDATION-PROMOTING COMPOSITIONS, METHODS OF FORMING OXIDE LAYERS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：氧化促进组合物，形成氧化物层的方法和制备半导体器件的方法
公开(公告)号：US20120058647A1
公开(公告)日：2012-03-08
申请号：US13224737
申请日：2011-09-02
申请人： Kyung-seok Oh , Kyung-mun Byun , Shin-hye Kim , Deok-young Jung , Gil-heyun Choi , Eunkee Hong
发明人： Kyung-seok Oh , Kyung-mun Byun , Shin-hye Kim , Deok-young Jung , Gil-heyun Choi , Eunkee Hong
IPC分类号： H01L21/316
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02326 , H01L21/76224
摘要： Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
摘要翻译：根据本发明的实施方案提供的是氧化促进组合物，形成氧化物层的方法和制造半导体器件的方法。在本发明的一些实施方案中，氧化促进组合物包括具有AML结构的氧化促进剂，其中L是化学吸附在硅表面，氧化硅，氮化硅或金属上的官能团，A是一种可热分解的氧化官能团，M是允许A和L彼此共价结合的部分。

5. 发明授权

US08354308B2 Conductive layer buried-type substrate, method of forming the conductive layer buried-type substrate, and method of fabricating semiconductor device using the conductive layer buried-type substrate 有权
标题翻译：导电层掩埋型基板，形成导电层掩埋型基板的方法以及使用导电层掩埋型基板制造半导体器件的方法
公开(公告)号：US08354308B2
公开(公告)日：2013-01-15
申请号：US13221158
申请日：2011-08-30
申请人： Pil-kyu Kang , Gil-heyun Choi , Dae-lok Bae , Byung-lyul Park , Dong-kak Lee
发明人： Pil-kyu Kang , Gil-heyun Choi , Dae-lok Bae , Byung-lyul Park , Dong-kak Lee
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66666 , H01L21/76254 , H01L21/84 , H01L27/10814 , H01L27/10876 , H01L27/10894 , H01L27/1203
摘要： A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.
摘要翻译：公开了一种导电层掩埋型衬底。基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上并且包括金属层和形成在导电层上的单晶半导体层。

6. 发明申请

US20130012023A1 METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME 有权
标题翻译：形成微孔板的方法，形成金刚石金属化的方法以及使用其制造的半导体器件和半导体存储器件
公开(公告)号：US20130012023A1
公开(公告)日：2013-01-10
申请号：US13533653
申请日：2012-06-26
申请人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
发明人： In-sun Park , Gil-heyun Choi , Ji-soon Park , Jong-myeong Lee , Jong-won Hong , Hei-seung Kim
IPC分类号： H01L21/308
CPC分类号： H01L23/48 , H01L21/0337 , H01L21/31144 , H01L21/3212 , H01L21/76816 , H01L23/522 , H01L27/11565 , H01L27/1157 , H01L29/06 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.
摘要翻译：根据示例性实施例，形成微图案的方法包括在衬底的虚拟区域上形成具有第一宽度的虚拟图案，并且在衬底的有源线区域上形成具有第二宽度的单元图案。有源线区域可以与虚拟区域相邻，并且第二宽度可以小于第一宽度。该方法可以进一步包括通过在有源线区域和虚拟区域上形成种子层来形成镶嵌金属化，在基片的整个表面上形成导电材料层，并平坦化导电材料层以形成金属线。

7. 发明授权

US08119526B2 Method of forming a metal layer and a method of fabricating a semiconductor device 有权
标题翻译：形成金属层的方法和制造半导体器件的方法
公开(公告)号：US08119526B2
公开(公告)日：2012-02-21
申请号：US12955093
申请日：2010-11-29
申请人： Eun-ji Jung , Woong-hee Sohn , Su-kyoung Kim , Gil-heyun Choi , Byung-hee Kim
发明人： Eun-ji Jung , Woong-hee Sohn , Su-kyoung Kim , Gil-heyun Choi , Byung-hee Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/28562
摘要： A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.
摘要翻译：一种形成金属膜的方法包括制备其上露出由第一金属形成的绝缘层和金属层的基板; 以及通过将第二金属的有机前体供给到所述基板上以同时在所述绝缘层和所述金属层上沉积所述第二金属而形成金属覆盖层，其中所述第二金属覆盖层在所述绝缘层和所述金属层上具有不同的厚度。

8. 发明授权

US07842600B2 Methods of forming interlayer dielectrics having air gaps 有权
标题翻译：形成具有气隙的层间电介质的方法
公开(公告)号：US07842600B2
公开(公告)日：2010-11-30
申请号：US12364598
申请日：2009-02-03
申请人： Jong-ho Yun , Jong-Myeong Lee , Gil-heyun Choi
发明人： Jong-ho Yun , Jong-Myeong Lee , Gil-heyun Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76849 , H01L2224/05026 , H01L2224/05639 , H01L2224/05669 , H01L2224/13 , H01L2924/00014 , H01L2224/05099
摘要： Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A metal wire is formed in the trench such that the metal wire is recessed beneath an upper surface of the first insulating layer. A metal layer is formed on the metal wire, wherein the metal layer includes a capping layer portion filling the recess, a upper portion formed on the capping layer portion, and an overhang portion formed on the portion of the first insulating layer adjacent to the trench protruding sideward from the upper portion. The first insulating layer is removed and a second insulating layer is formed on the semiconductor substrate to cover the metal layer, whereby an air gap is formed below the overhang portion of the metal layer. A portion of the second insulating layer is removed to expose the upper portion of the metal layer. The upper portion and the overhang portion of the metal layer are removed. A third insulating layer is formed on the semiconductor substrate from which the upper portion and the overhang portion have been removed to maintain the air gap.
摘要翻译：提供了形成具有气隙的层间电介质的方法，包括在半导体衬底上形成第一绝缘层。第一绝缘层限定沟槽。在沟槽中形成金属线，使得金属线在第一绝缘层的上表面下方凹入。在金属线上形成金属层，其中金属层包括填充凹部的覆盖层部分，形成在覆盖层部分上的上部，和形成在与沟槽相邻的第一绝缘层的部分上的突出部分从上部侧向突出。去除第一绝缘层，并且在半导体衬底上形成覆盖金属层的第二绝缘层，由此在金属层的伸出部分的下方形成气隙。去除第二绝缘层的一部分以露出金属层的上部。去除金属层的上部和外伸部分。在半导体基板上形成第三绝缘层，从该基板上去除上部和外伸部分以保持气隙。

9. 发明申请

US20100193902A1 SEMICONDUCTOR DEVICE INCLUDING FUSE 有权
标题翻译：包括保险丝的半导体器件
公开(公告)号：US20100193902A1
公开(公告)日：2010-08-05
申请号：US12502490
申请日：2009-07-14
申请人： Seung-woo SHIN , Byung-Iyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
发明人： Seung-woo SHIN , Byung-Iyul Park , Jong-myeong Lee , Gil-heyun Choi , Jong-ho Yun
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.
摘要翻译：提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层，除了保护层。

10. 发明申请

US20090325371A1 Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes 有权
标题翻译：形成具有堆叠栅电极的集成电路器件的方法
公开(公告)号：US20090325371A1
公开(公告)日：2009-12-31
申请号：US12424922
申请日：2009-04-16
申请人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
发明人： Byung-hee Kim , Gil-heyun Choi , Sang-woo Lee , Chang-won Lee , Jin-ho Park , Eun-ji Jung , Jeong-gil Lee
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/66545
摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
摘要翻译：提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

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