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1. 发明授权

US07877717B2 Accurately modeling an asynchronous interface using expanded logic elements 有权
标题翻译：使用扩展的逻辑元素精确地建模异步接口
公开(公告)号：US07877717B2
公开(公告)日：2011-01-25
申请号：US11874620
申请日：2007-10-18
申请人： Bing-Lun Chu , Yee Ja , Bradley S. Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley S. Nelson , Wolfgang Roesner
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022 , G06F17/5031
摘要： Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了使用扩展逻辑元件对异步接口进行精确建模的机制。利用这些机制，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或毛刺危险，以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

2. 发明申请

US20060190858A1 System and method for accurately modeling an asynchronous interface using expanded logic elements 失效
标题翻译：使用扩展逻辑元素对异步接口进行精确建模的系统和方法
公开(公告)号：US20060190858A1
公开(公告)日：2006-08-24
申请号：US11054880
申请日：2005-02-10
申请人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或毛刺危险，以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

3. 发明申请

US20080040695A1 System and Method for Accurately Modeling an Asynchronous Interface using Expanded Logic Elements 有权
标题翻译：使用扩展逻辑元件精确建模异步接口的系统和方法
公开(公告)号：US20080040695A1
公开(公告)日：2008-02-14
申请号：US11874620
申请日：2007-10-18
申请人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或故障危险以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

4. 发明授权

US07299436B2 System and method for accurately modeling an asynchronous interface using expanded logic elements 失效
标题翻译：使用扩展逻辑元素对异步接口进行精确建模的系统和方法
公开(公告)号：US07299436B2
公开(公告)日：2007-11-20
申请号：US11054880
申请日：2005-02-10
申请人： Bing-Lun Chu , Yee Ja , Bradley S. Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley S. Nelson , Wolfgang Roesner
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或毛刺危险，以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

5. 发明授权

US4093971A D-I-P On island 失效
标题翻译： D-I-P岛上
公开(公告)号：US4093971A
公开(公告)日：1978-06-06
申请号：US748837
申请日：1976-12-10
申请人： Bing-Lun Chu , Wunnava Venkata Subbarao , Jack Peale , Kent McCune , Marvin Elroy Steiner
发明人： Bing-Lun Chu , Wunnava Venkata Subbarao , Jack Peale , Kent McCune , Marvin Elroy Steiner
IPC分类号： H01L23/40 , H01L23/433 , H01L23/473 , H05K7/20
CPC分类号： H01L23/473 , H01L23/4006 , H01L23/433 , H05K7/20445 , H01L2023/405 , H01L2023/4062 , H01L2924/0002 , H01L2924/3011
摘要： A cooling system for integrated circuit packaging of the conventional dual-in-line (DIP) type, including a cold bar which engages the DIPs and is thermally and mechanically connected at both ends to a cooling frame in which a serpentine tubing carries coolant throughout spaced-apart sections thereof. Clamping means clamp the DIPs tight against the cold bar so that heat generated by the DIPs is carried away through the cold bar into the frame sections where the coolant circulates. The cold bar is disposed so that discrete components may be disposed on the island in a manner to save lateral space, and a multiplicity of these DIPs, cold bars, etc. are mounted on the cooling frame to form a DIP island cooling frame and may include, for example, driver buffer logic, random access memories, as well as I/O logic. Each DIP island can be connected to a cooling frame having other types of integrated circuits and housed in the same console or housed along with similar DIP islands in a similar console, as desired.
摘要翻译：一种用于常规双列直插式（DIP）型集成电路封装的冷却系统，包括接合DIP的冷棒，并在两端热连接和机械连接到一个冷却框架，其中蛇形管道将冷却剂沿间隔其部分。夹紧装置将DIP紧固在冷杆上，使得DIP产生的热量通过冷却杆被带走到冷却剂循环的框架部分。冷棒被设置成使得分立的部件可以以节省横向空间的方式设置在岛上，并且多个这些DIP，冷棒等安装在冷却框架上以形成DIP岛冷却框架，并且可以包括例如驱动器缓冲器逻辑，随机存取存储器以及I / O逻辑。每个DIP岛可以连接到具有其他类型的集成电路的冷却框架，并且根据需要容纳在相同的控制台中或与类似的控制台中的类似DIP岛一起容纳。

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