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1. 发明授权

US07932761B1 Fine tuned pulse width modulation 有权
标题翻译：微调脉宽调制
公开(公告)号：US07932761B1
公开(公告)日：2011-04-26
申请号：US12368264
申请日：2009-02-09
申请人： Benjamin Esposito
发明人： Benjamin Esposito
IPC分类号： H03K3/017
CPC分类号： H03K7/08
摘要： Techniques and an apparatus for producing pulse width modulation (PWM) edges are described. A PWM controller circuit with a polyphase counter is described. The polyphase counter may comprise a plurality of counters. Each of the counters may be set to a specific initial count value. A polyphase decoder block with a plurality of sets of high/low decoders are coupled to outputs from the polyphase counter. A set/reset block with a plurality of set/reset logic elements is coupled to outputs from the polyphase decoder block. A serializer is coupled to outputs from the plurality of set/reset blocks to generate PWM edges. Multiple parallel phases of a PWM pulse may be created with the circuit. Using a polyphase counter and comparator to create multiple parallel phases may speed up the controller circuit and provide a finer tuning resolution.
摘要翻译：描述了用于产生脉冲宽度调制（PWM）边缘的技术和装置。描述了具有多相计数器的PWM控制器电路。多相计数器可以包括多个计数器。每个计数器可以被设置为特定的初始计数值。具有多组高/低解码器的多相解码器模块耦合到来自多相计数器的输出。具有多个设置/复位逻辑元件的置位/复位块耦合到来自多相解码器块的输出。串行器耦合到来自多个设置/复位块的输出以产生PWM边缘。可以用电路产生PWM脉冲的多个并联相位。使用多相计数器和比较器创建多个并联相位可以加快控制器电路并提供更精细的调谐分辨率。

2. 发明授权

US07864080B1 Sample rate conversion by controlled selection of filter outputs 有权
标题翻译：通过控制选择滤波器输出进行采样率转换
公开(公告)号：US07864080B1
公开(公告)日：2011-01-04
申请号：US12345045
申请日：2008-12-29
申请人： Suleyman Sirri Demirsoy , Lawrence Rigby , Benjamin Esposito
发明人： Suleyman Sirri Demirsoy , Lawrence Rigby , Benjamin Esposito
IPC分类号： H03M7/00 , G06F17/17
CPC分类号： H03H17/0685 , H03H17/0275
摘要： A sample rate converter in which filtering is decomposed into phases as permitted by zero padding is described. The outputs of the phases are issued in the correct sequence to provide the resampled sequence.
摘要翻译：描述了一种采样率转换器，其中滤波被零填充所允许的分解成相位。相位的输出以正确的顺序发出以提供重采样序列。

3. 发明授权

US07356554B1 Variable fixed multipliers using memory blocks 失效
标题翻译：使用内存块的可变固定乘数
公开(公告)号：US07356554B1
公开(公告)日：2008-04-08
申请号：US11168984
申请日：2005-06-27
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/42 , H03K19/177
CPC分类号： G06F7/5324 , G06F7/4806
摘要： A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
摘要翻译：可编程逻辑器件包括至少一个产生第一多位计算结果的RAM块，其可以但不一定涉及两个操作数的乘法。由第二多位计算结果驱动的移位操作将第二多位计算结果移位至少一位以产生移位的第二多位计算结果。耦合到至少一个RAM块的多位加法器将移位的第二多位计算结果与第一多位计算结果相加。

4. 发明授权

US07598790B1 Clock synthesis using polyphase numerically controlled oscillator 有权
标题翻译：使用多相数控振荡器的时钟合成
公开(公告)号：US07598790B1
公开(公告)日：2009-10-06
申请号：US12022934
申请日：2008-01-30
申请人： Benjamin Esposito , Hong Shan Neoh
发明人： Benjamin Esposito , Hong Shan Neoh
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/08
摘要： A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.
摘要翻译：时钟合成电路包括多相数控振荡器，提取电路和时钟信号发生电路。多相数控振荡器产生一组周期性输出信号。每组周期性输出信号表示周期波形信号的不同相位。提取电路从多相数字控制振荡器的每组周期性输出信号中提取最高有效位以产生最高有效位。时钟信号产生电路将最高有效位转换成用作输出时钟信号的串行比特流。

5. 发明授权

US07269617B1 Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry 有权
标题翻译：使用DSP电路和可编程逻辑电路实现的混合乘法器
公开(公告)号：US07269617B1
公开(公告)日：2007-09-11
申请号：US10712500
申请日：2003-11-12
申请人： Benjamin Esposito , Robert L Pelt
发明人： Benjamin Esposito , Robert L Pelt
IPC分类号： G06F7/523
CPC分类号： G06F7/53 , G06F7/5443 , G06F2207/3816 , H03K19/17732
摘要： A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.
摘要翻译：提供了一种用于硬件应用的用户逻辑设计，其在PLD中有效地实现了使用嵌入在PLD中集成的DSP电路中的可编程逻辑电路和一个或多个乘法器的用户逻辑设计乘法器。可以通过在部分产品布置的总和中实现用户逻辑设计乘数来使用较小的DSP乘法器，其中使用较小的DSP乘法器生成部分乘积之一，其余部分乘积由使用可编程逻辑电路实现的乘法器生成。

6. 发明授权

US06943579B1 Variable fixed multipliers using memory blocks 失效
标题翻译：使用内存块的可变固定乘数
公开(公告)号：US06943579B1
公开(公告)日：2005-09-13
申请号：US10668449
申请日：2003-09-22
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/42 , G06F7/523 , H03K19/177
CPC分类号： G06F7/523 , G06F2207/4802
摘要： A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
摘要翻译：可编程逻辑器件包括至少一个产生第一多位计算结果的RAM块，其可以但不一定涉及两个操作数的乘法。由第二多位计算结果驱动的移位操作将第二多位计算结果移位至少一位以产生移位的第二多位计算结果。耦合到至少一个RAM块的多位加法器将移位的第二多位计算结果与第一多位计算结果相加。

7. 发明授权

US07987222B1 Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension 有权
标题翻译：用于实现利用数字信号处理器块存储器扩展的乘法器的方法和装置
公开(公告)号：US07987222B1
公开(公告)日：2011-07-26
申请号：US10829559
申请日：2004-04-22
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , H03K19/1733
摘要： A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
摘要翻译：用于在现场可编程门阵列上执行乘法的方法包括通过将来自第一数字的第一多个比特和来自第二个数的第一多个比特相乘来产生乘积。检索从第一个数字指定为第二个多个位的乘积的存储值和来自第二个数字的第二个多个位。相对于来自第一数量的第一多个比特的位置和来自第二个数字的第一多个比特的位置来对该乘积进行缩放。所存储的值相对于来自第二数量的第二多个比特的位置和第二多个比特的位置从第二个数字缩放。将缩放的产品和缩放的存储值相加。

8. 发明授权

US07949699B1 Implementation of decimation filter in integrated circuit device using ram-based data storage 有权
标题翻译：在使用基于RAM的数据存储的集成电路设备中实现抽取滤波器
公开(公告)号：US07949699B1
公开(公告)日：2011-05-24
申请号：US11848020
申请日：2007-08-30
申请人： Hong Shan Neoh , Benjamin Esposito
发明人： Hong Shan Neoh , Benjamin Esposito
IPC分类号： G06F17/10
CPC分类号： H03H17/0664 , H03H17/0223 , H03H17/0225 , H03H2017/0298 , H03H2218/085
摘要： A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.
摘要翻译：诸如可编程逻辑器件的可编程集成电路器件可被配置为能够以抽取模式操作的有限脉冲响应（FIR）滤波器。该设备包括至少一个用户可配置的随机存取存储器块，并且该用户可配置的随机存取存储器被配置为系数存储器和数据采样存储器。存储器足够大以一次保持到滤波器的所有系数和多个数据样本。因为数据样本和系数不需要以可编程逻辑器件时钟速率移动通过滤波器，因此滤波器的超频不是必需的。滤波器可以以与输入数据速率相同的时钟速率运行，同时利用可用的随机存取存储器来模拟移位寄存器。

9. 发明授权

US07793013B1 High-speed FIR filters in FPGAs 有权
标题翻译： FPGA中的高速FIR滤波器
公开(公告)号：US07793013B1
公开(公告)日：2010-09-07
申请号：US11323387
申请日：2005-12-29
申请人： Benjamin Esposito
发明人： Benjamin Esposito
IPC分类号： G06F13/00
CPC分类号： H03H17/06 , H03H17/0223 , H03H2017/0247
摘要： Methods, circuits, and an apparatus for filtering high-speed serial data is disclosed. In one embodiment, a Programmable Logic Device (PLD) is configured with a filter circuit for filtering serial data at a first clock rate. The filter circuit converts an N number of serial data streams into an N number of M-bit words based on a deserialization factor. The M-bit words are converted to an M number of N-bit data words. The N-Bit data words are filtered at a second clock rate, reformatted, serialized, and outputted as individual serial data streams at the first clock rate. In one embodiment, the N-bit data words are digitally filtered by a Finite Impulse Response (FIR) filter operating at the second clock rate. The data output of the FIR filter is then serialized into an N number of serial data output streams operating at the first clock rate.
摘要翻译：公开了用于过滤高速串行数据的方法，电路和装置。在一个实施例中，可编程逻辑器件（PLD）配置有用于以第一时钟速率对串行数据进行滤波的滤波器电路。滤波器电路基于反序列化因子将N个串行数据流转换成N个M比特字。 M位字被转换成M个N位数据字。以第二时钟速率对N位数据字进行滤波，重新格式化，串行化并以第一时钟速率作为单独的串行数据流输出。在一个实施例中，N位数据字由以第二时钟速率操作的有限脉冲响应（FIR）滤波器进行数字滤波。然后将FIR滤波器的数据输出串行化为以第一时钟速率工作的N个串行数据输出流。

10. 发明授权

US07570120B1 Multichannel memory-based numerically controlled oscillators 有权
标题翻译：基于多通道存储器的数控振荡器
公开(公告)号：US07570120B1
公开(公告)日：2009-08-04
申请号：US11820268
申请日：2007-06-18
申请人： Benjamin Esposito
发明人： Benjamin Esposito
IPC分类号： H03L7/085 , H03K19/177
CPC分类号： H03K19/17732 , G06F1/0342
摘要： A multichannel numerically controlled oscillator is provided. The multichannel numerically controlled oscillator has a dual port memory. An output function generation lookup table in the dual port memory is used to generate output functions for the numerically controlled oscillator. A first channel of output is generated based on a first address signal that is presented on a first port of the dual port memory. A second channel of output is generated based on a second address signal that is presented on a second port of the dual port memory. First and second phase accumulators may be used to produce the address signals for the first and second ports of the dual port memory, respectively. The phase accumulators may each contain a register, an adder, and a feedback path. The registers in the phase accumulators and the dual port memory may handle signals at the clock rate of the output channels.
摘要翻译：提供多通道数控振荡器。多通道数控振荡器具有双端口存储器。双端口存储器中的输出函数生成查找表用于产生数控振荡器的输出功能。基于在双端口存储器的第一端口上呈现的第一地址信号来产生第一输出通道。基于在双端口存储器的第二端口上呈现的第二地址信号来产生第二输出通道。第一和第二相位累加器可以分别用于产生双端口存储器的第一和第二端口的地址信号。相位累加器可以各自包含寄存器，加法器和反馈路径。相位累加器和双端口存储器中的寄存器可以以输出通道的时钟速率处理信号。

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