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1. 发明授权

US06943579B1 Variable fixed multipliers using memory blocks 失效
标题翻译：使用内存块的可变固定乘数
公开(公告)号：US06943579B1
公开(公告)日：2005-09-13
申请号：US10668449
申请日：2003-09-22
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/42 , G06F7/523 , H03K19/177
CPC分类号： G06F7/523 , G06F2207/4802
摘要： A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
摘要翻译：可编程逻辑器件包括至少一个产生第一多位计算结果的RAM块，其可以但不一定涉及两个操作数的乘法。由第二多位计算结果驱动的移位操作将第二多位计算结果移位至少一位以产生移位的第二多位计算结果。耦合到至少一个RAM块的多位加法器将移位的第二多位计算结果与第一多位计算结果相加。

2. 发明授权

US07987222B1 Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension 有权
标题翻译：用于实现利用数字信号处理器块存储器扩展的乘法器的方法和装置
公开(公告)号：US07987222B1
公开(公告)日：2011-07-26
申请号：US10829559
申请日：2004-04-22
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , H03K19/1733
摘要： A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
摘要翻译：用于在现场可编程门阵列上执行乘法的方法包括通过将来自第一数字的第一多个比特和来自第二个数的第一多个比特相乘来产生乘积。检索从第一个数字指定为第二个多个位的乘积的存储值和来自第二个数字的第二个多个位。相对于来自第一数量的第一多个比特的位置和来自第二个数字的第一多个比特的位置来对该乘积进行缩放。所存储的值相对于来自第二数量的第二多个比特的位置和第二多个比特的位置从第二个数字缩放。将缩放的产品和缩放的存储值相加。

3. 发明授权

US07356554B1 Variable fixed multipliers using memory blocks 失效
标题翻译：使用内存块的可变固定乘数
公开(公告)号：US07356554B1
公开(公告)日：2008-04-08
申请号：US11168984
申请日：2005-06-27
申请人： Asher Hazanchuk , Benjamin Esposito
发明人： Asher Hazanchuk , Benjamin Esposito
IPC分类号： G06F7/42 , H03K19/177
CPC分类号： G06F7/5324 , G06F7/4806
摘要： A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
摘要翻译：可编程逻辑器件包括至少一个产生第一多位计算结果的RAM块，其可以但不一定涉及两个操作数的乘法。由第二多位计算结果驱动的移位操作将第二多位计算结果移位至少一位以产生移位的第二多位计算结果。耦合到至少一个RAM块的多位加法器将移位的第二多位计算结果与第一多位计算结果相加。

4. 发明申请

US20060053192A1 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices 失效
公开(公告)号：US20060053192A1
公开(公告)日：2006-03-09
申请号：US11264778
申请日：2005-10-31
申请人： Chang Choo , Asher Hazanchuk
发明人： Chang Choo , Asher Hazanchuk
IPC分类号： G06F7/38
CPC分类号： G06F1/03 , G06F2101/12 , G06F2101/16 , H03K19/1733
摘要： Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

5. 发明授权

US09535705B1 Flexible hardware programmable scalable parallel processor 有权
标题翻译：灵活的硬件可编程可扩展并行处理器
公开(公告)号：US09535705B1
公开(公告)日：2017-01-03
申请号：US14458972
申请日：2014-08-13
申请人： Asher Hazanchuk
发明人： Asher Hazanchuk
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F15/7867
摘要： In a typical embodiment, a parallel processor is provided that includes:A plurality of parallel processing units that are interconnected to provide a flexible hardware programmable, scalable and re-configurable parallel processor that executes different functions in a parallel processor space domain instead of a processor (serial processor) time domain. Each parallel processing unit includes a flexible processing engine with its inputs and outputs connected to MDDP-RAM blocks. The MDDP-RAM blocks provide the processing engine with different channels' data and coefficients. The processing engine and the MDDP-RAM blocks are controlled by a system processor (or other control scheme hardware) via the parameter blocks to enable high hardware flexibility and software programmability.
摘要翻译：多个并行处理单元，其互连以提供在并行处理器空间域而不是处理器（串行处理器）时域中执行不同功能的灵活的硬件可编程，可扩展和可重新配置的并行处理器。每个并行处理单元包括一个灵活的处理引擎，其输入和输出连接到MDDP-RAM块。 MDDP-RAM块为处理引擎提供不同通道的数据和系数。处理引擎和MDDP-RAM块通过参数块由系统处理器（或其他控制方案硬件）控制，以实现高硬件灵活性和软件可编程性。

6. 发明授权

US07348914B1 Method and systems to align outputs signals of an analog-to-digital converter 有权
标题翻译：对准模拟 - 数字转换器的输出信号的方法和系统
公开(公告)号：US07348914B1
公开(公告)日：2008-03-25
申请号：US11477759
申请日：2006-06-29
申请人： Asher Hazanchuk , Ian Ing , Satwant Singh
发明人： Asher Hazanchuk , Ian Ing , Satwant Singh
IPC分类号： H03M1/12
CPC分类号： H03M1/124 , H03M1/1215
摘要： Systems and methods are disclosed herein to provide improved alignment of output signals of an analog-to-digital converter (ADC). For example, in accordance with an embodiment of the present invention, a method of aligning digital signals appearing on signal paths of a parallel data bus includes sampling the digital signals at a plurality of delay times to obtain a plurality of sample sets, wherein each sample set is associated with a corresponding delay time. A second digital signal that is misaligned with respect to a first digital signal is identified from the sample sets. The delay time required to align the second digital signal with the first digital signal is determined. The delay of the second digital signal is adjusted by the determined delay time.
摘要翻译：本文公开了系统和方法以提供模数转换器（ADC）的输出信号的改进对准。例如，根据本发明的实施例，对并行数据总线的信号路径上出现的数字信号进行对准的方法包括以多个延迟时间对数字信号进行采样以获得多个样本集，其中每个样本设置与相应的延迟时间相关联。从样本集中识别相对于第一数字信号不对准的第二数字信号。确定将第二数字信号与第一数字信号对准所需的延迟时间。第二数字信号的延迟由确定的延迟时间进行调整。

7. 发明申请

US20060277240A1 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices 审中-公开
标题翻译：用于在可编程逻辑器件中实现高效运算电路的装置和方法
公开(公告)号：US20060277240A1
公开(公告)日：2006-12-07
申请号：US11504849
申请日：2006-08-16
申请人： Chang Choo , Asher Hazanchuk
发明人： Chang Choo , Asher Hazanchuk
IPC分类号： G06F7/38
CPC分类号： G06F1/03 , G06F2101/12 , G06F2101/16 , H03K19/1733
摘要： Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.
摘要翻译：通过使用查找表（LUT）来存储预先计算的值，可编程逻辑器件中算术电路的有效实现。执行表查找操作来代替复杂的算术运算。以这种方式，以牺牲几个LUT为代价，可以节省许多逻辑元素。该方法特别适用于用于计算互逆值的电路和用于执行归一化LMS算法的电路。

8. 发明授权

US07058675B1 Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices 失效
公开(公告)号：US07058675B1
公开(公告)日：2006-06-06
申请号：US09863650
申请日：2001-05-22
申请人： Chang Choo , Asher Hazanchuk
发明人： Chang Choo , Asher Hazanchuk
IPC分类号： G06F1/02 , G06F7/52
CPC分类号： G06F1/03 , G06F2101/12 , G06F2101/16 , H03K19/1733
摘要： Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.

9. 发明授权

US06888372B1 Programmable logic device with soft multiplier 有权
标题翻译：具有软乘法器的可编程逻辑器件
公开(公告)号：US06888372B1
公开(公告)日：2005-05-03
申请号：US10326652
申请日：2002-12-20
申请人： Asher Hazanchuk
发明人： Asher Hazanchuk
IPC分类号： G06F7/42 , G06F7/523 , H03K19/177
CPC分类号： G06F7/523 , G06F2207/4802
摘要： A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. First programmable logic circuitry is programmed to operate as a shift register with multiple tap outputs to multiple first address registers. Second programmable logic circuitry is programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output.
摘要翻译：提供了一种可编程逻辑器件，其包括具有包括第一地址寄存器和第一数据寄存器的第一端口以及包括第二地址寄存器和第二数据寄存器的第二端口的多端口RAM块。至少一个查找表存储在RAM块中。第一个可编程逻辑电路被编程为具有多个抽头输出的移位寄存器用于多个第一地址寄存器。第二可编程逻辑电路被编程为作为累加电路操作，其包括耦合到多个第一数据寄存器并包括累加器输出的多位输入。

10. 发明授权

US08977885B1 Programmable logic device data rate booster for digital signal processing 有权
标题翻译：用于数字信号处理的可编程逻辑器件数据速率增强器
公开(公告)号：US08977885B1
公开(公告)日：2015-03-10
申请号：US13412408
申请日：2012-03-05
申请人： Asher Hazanchuk
发明人： Asher Hazanchuk
IPC分类号： G06F1/04 , G06F5/06
CPC分类号： G06F7/5443 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.
摘要翻译：提供了一种可编程逻辑器件，其包括：可编程互连，其适于以系统时钟速率路由输入信号通过所述器件; 以及耦合到所述互连的数字信号处理器（DSP）块，所述DSP块包括：多个输入端口; 输入寄存器，其耦合到所述多个输入端口，并且适于以所述系统时钟速率的倍数顺序地登记在所述输入端口处接收的所述互连的输入信号的采样; 以及适于以所述系统时钟速率的倍数乘以所述注册的采样以产生输出信号的乘法器。

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