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1. 发明申请

US20050055615A1 At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform 有权
标题翻译：使用VLCT测试平台的高速ATPG测试和SoC设计的设备具有多个时钟域
公开(公告)号：US20050055615A1
公开(公告)日：2005-03-10
申请号：US10731714
申请日：2003-12-09
申请人： Anupama Agashe , Nikila Krishnamoorthy , Anlndya Saha , Rubin Parekhji
发明人： Anupama Agashe , Nikila Krishnamoorthy , Anlndya Saha , Rubin Parekhji
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318552
摘要： A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.
摘要翻译：本文公开了嵌入在具有VLCT平台的扫描架构的SoC上的扫描测试电路设计。该BIST电路设计不受所支持的扫描测试端口数量的限制，包括至少一个具有耦合以接收测试激励数据的相应时钟域的扫描链组。每个扫描链组具有对应的测试模式信号，以从其对应的时钟域导出的移位时钟速率移动测试激励数据。控制解复用器连接到每个扫描链组内的每个多路复用器单元，以提供用于在测试刺激中移位的控制信号。时钟控制机制为每个扫描链提供控制信号，以移动测试刺激并捕获结果数据。此外，当启用同时测试模式信号时，时钟控制机制耦合到每个扫描链以实现每个扫描链组的同时捕获。

2. 发明申请

US20050066243A1 Mechanism to enhance observability of integrated circuit failures during burn-in tests 有权
标题翻译：增强烧录测试期间集成电路故障的可观察性的机制
公开(公告)号：US20050066243A1
公开(公告)日：2005-03-24
申请号：US10667879
申请日：2003-09-22
申请人： Gordhan Barevadia , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji , Neil Simpson
发明人： Gordhan Barevadia , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji , Neil Simpson
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G11C29/44
CPC分类号： G11C29/44 , G01R31/2856 , G01R31/318577 , G01R31/31905 , G11C2029/3202 , G11C2029/3602
摘要： A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
摘要翻译：系统和方法提高了老化测试期间IC故障的可观察性。扫描自动测试模式生成和内存自检模式在老化测试期间被监控，以提供观察选择性扫描链输出和存储器BIST状态输出的机制。

3. 发明申请

US20050065747A1 Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components 有权
标题翻译：混合信号核心设计，用于混合信号，模拟和数字组件的并发测试
公开(公告)号：US20050065747A1
公开(公告)日：2005-03-24
申请号：US10677150
申请日：2003-10-01
申请人： Amit Premy , Vudutha Suresh Gupta , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji
发明人： Amit Premy , Vudutha Suresh Gupta , Anupama Agashe , Nikila Krishnamoorthy , Rubin Parekhji
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/3167 , G01R31/317 , G01R31/3185 , G06F19/00 , G06J1/00
CPC分类号： G06J1/00 , G01R31/3167 , G01R31/31704 , G01R31/3172 , G01R31/318533
摘要： A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, wherein the first mode of operation provides digital interface characterization testing of the first and second digital module and analog characterization/trimming testing of the analog module. In the second mode of operation, concurrent testing of the analog module and the first and second digital module is conducted; wherein analog characterization/trimming testing is performed on the analog module and digital interface characterization testing is performed on the first digital module, while SCAN/BIST testing is performed on the second digital module. In the third mode of operation, non-concurrent testing of the analog module, the first digital module, and the second digital module is enabled; wherein SCAN/BIST testing of the first digital module and the second digital module is enabled, while the analog module is powered down.
摘要翻译：本文公开的混合信号芯片被设计用于有效并发测试模拟，混合信号和数字组件。一个测试人员可以测试所有组件，从而减少测试时间，而不会损失完整的测试覆盖范围。模拟模块包括混合信号核心的所有模拟和混合信号组件，而第一数字模块包括模拟量模块内混合信号组件的功能/参数验证所需的数字组件。第一个虚拟边界将模拟和第一个数字模块连接起来，以在测试期间对信号传输进行门控。第二数字模块包括混合信号核心的剩余数字分量，由此第二虚拟边界将其与第一数字模块分离。这种分区使得混合信号核心具有三种操作模式，其中第一操作模式提供第一和第二数字模块的数字接口表征测试以及模拟模块的模拟表征/修整测试。在第二种操作模式下，对模拟模块和第一和第二数字模块进行并行测试; 其中对模拟模块执行模拟表征/修整测试，并且在第一数字模块上执行数字接口表征测试，同时在第二数字模块上执行扫描/ BIST测试。在第三种操作模式下，模拟模块，第一个数字模块和第二个数字模块的非并发测试被启用; 其中模拟模块被断电时，启用第一数字模块和第二数字模块的扫描/ BIST测试。

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