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1. 发明授权

US5994910A Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips 失效
标题翻译：装置及相应的方法，用于应力测试导线接合型半导体芯片
公开(公告)号：US5994910A
公开(公告)日：1999-11-30
申请号：US160057
申请日：1998-09-24
申请人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
IPC分类号： G01R31/28 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2862
摘要： An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.
摘要翻译：公开了一种用于应力测试引线接合型半导体芯片的装置和相应的方法。该装置包括夹紧壳体，其中弹簧加载的螺钉延伸穿过壳体的顶端。包含在夹具壳体内的是位于夹具壳体的下端的基本上刚性的电绝缘基板。基板的上表面包括凹陷，其包含由弹性体材料或诸如硅的半导体材料制成的插入件。由例如聚酰亚胺制成的柔性电绝缘层覆盖在基板和插入件上。重要的是，柔性电绝缘层的上表面包括多个树枝状接触。通过这些树突状触点，对引线接合型半导体芯片的接触焊盘进行电接触。

2. 发明授权

US5672980A Method and apparatus for testing integrated circuit chips 失效
标题翻译：用于测试集成电路芯片的方法和装置
公开(公告)号：US5672980A
公开(公告)日：1997-09-30
申请号：US602167
申请日：1996-02-15
申请人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
发明人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R1/0483 , G01R1/07307 , G01R31/2863 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.
摘要翻译：公开了一种用于测试半导体芯片的方法和装置。单个半导体芯片具有I / O触点。该装置设置有具有对应于半导体芯片上的触点的触点的插入器。芯片和内插器触点都可以是任何已知的类型，包括金属球，凸块或凸片，或者可以设置有树枝状表面。首先将芯片触点与插入件上的触点进行相对松动的临时接触，然后将大于每芯片接触5克的压缩力施加到芯片上以迫使芯片触头与插入器触点良好地电接触。然后进行芯片的测试。测试可能包括加热芯片以及将信号应用于芯片触点。测试后，芯片从基板上取下。

3. 发明授权

US06414509B1 Method and apparatus for in-situ testing of integrated circuit chips 失效
标题翻译：用于集成电路芯片现场测试的方法和装置
公开(公告)号：US06414509B1
公开(公告)日：2002-07-02
申请号：US09564652
申请日：2000-05-03
申请人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
发明人： Anilkumar Chinuprasad Bhatt , Leo Raymond Buda , Robert Douglas Edwards , Paul Joseph Hart , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla , Richard Gerald Murphy , George John Saxenmeyer, Jr. , George Frederick Walker , Bette Jaye Whalen , Richard Stuart Zarr
IPC分类号： G01R3102
CPC分类号： H01L24/81 , G01R31/2886 , H01L22/20 , H01L24/75 , H01L2224/0401 , H01L2224/05557 , H01L2224/13111 , H01L2224/75 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
摘要翻译：公开了半导体芯片的测试方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一个芯片载体。芯片载体具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片载体上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。在测试之后，芯片可以从衬底去除。或者，芯片可以在成功测试之后通过树枝状导体焊盘粘合到衬底上。

4. 发明授权

US6150255A Method of planarizing a curved substrate and resulting structure 失效
标题翻译：平面化弯曲基板和结构的方法
公开(公告)号：US6150255A
公开(公告)日：2000-11-21
申请号：US373868
申请日：1999-08-13
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.
摘要翻译：根据本发明，提供了一种用于为平坦化基板提供焊球，特别是多层陶瓷基板的树枝状连接的技术。在衬底在顶表面上具有凸起的中心部分的情况下，其上设置有顶表面冶金衬垫，一层适形的可光成像材料放置在顶表面上。可光成像材料以对应于顶表面冶金垫的图案的图案曝光和显影，以在可光成像材料中形成通孔。将铜镀在与顶部表面冶金垫接触的通孔中。然后将光致变形表面的暴露表面平坦化，优选通过机械抛光以形成平坦的平坦表面，其中通孔的端部暴露。然后，树枝状连接器焊盘在I / C芯片的焊球连接可释放地连接到的通孔的暴露端上生长。

5. 发明授权

US5709336A Method of forming a solderless electrical connection with a wirebond chip 失效
标题翻译：用引线芯片形成无焊接电连接的方法
公开(公告)号：US5709336A
公开(公告)日：1998-01-20
申请号：US656628
申请日：1996-05-31
申请人： Anthony Paul Ingraham , William Tze-You Chen
发明人： Anthony Paul Ingraham , William Tze-You Chen
IPC分类号： G01R31/28 , H01L21/60 , H01L21/66 , H01L23/498 , H05K3/32 , H05K3/40
CPC分类号： H01L22/20 , G01R31/2886 , H01L23/49816 , H01L24/81 , H01L2224/0401 , H01L2224/05571 , H01L2224/13019 , H01L2224/13144 , H01L2224/45144 , H01L2224/81801 , H01L2924/01013 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K3/325 , H05K3/4007 , Y10T29/4913
摘要： A dendrite surface is provided on each of the electrical contacts of a substrate, such as a test board, chip carrier, or printed wiring board. The electrical contacts on the substrate are arranged in a mirror image of the input/output pads on a wirebond chip from which the wire leads have been removed from, or not initially provided on, each of the input/output pads. The wirebond chip is aligned with the substrate, and the respective contact brought into electrical communication with each other. The wirebond chip may be removed after testing or other temporary attachment purpose, or permanently encapsulated with at least a portion of the substrate in a permanent assembly. The present invention permits wirebond chips to be selectively attached temporarily or permanently, i.e., have a pluggable capability, as well as the ability to allow a full array of I/O pad design.
摘要翻译：在诸如测试板，芯片载体或印刷线路板之类的基板的每个电触头上设置有枝晶表面。衬底上的电接触被布置在引线键合上的输入/输出焊盘的镜像中，引线已经从该引线引出已从每个输入/输出焊盘移除，或者不是最初设置在其上。引线键合芯片与衬底对准，并且相应的触点彼此电连通。引线键芯可以在测试或其它临时附接目的之后移除，或者在永久组件中与基底的至少一部分永久封装。本发明允许引线键盘临时或永久地选择性地附接，即具有可插拔能力，以及允许完整阵列的I / O焊盘设计的能力。

6. 发明授权

US5940729A Method of planarizing a curved substrate and resulting structure 失效
公开(公告)号：US5940729A
公开(公告)日：1999-08-17
申请号：US633984
申请日：1996-04-17
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

7. 发明授权

US5659256A Method and apparatus for testing integrated circuit chips 失效
公开(公告)号：US5659256A
公开(公告)日：1997-08-19
申请号：US601923
申请日：1996-02-15
申请人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
发明人： Richard Gordon Charlton , George Charles Correia , Mark Andrew Couture , Gary Ray Hill , Kibby Barth Horsford , Anthony Paul Ingraham , Michael David Lowell , Voya Rista Markovich , Gordon Charles Osborne, Jr. , Mark Vincent Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R1/0483 , G01R1/07307 , G01R31/2863 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

8. 发明授权

US5759046A Dendritic interconnection system 失效
标题翻译：树枝状互连系统
公开(公告)号：US5759046A
公开(公告)日：1998-06-02
申请号：US773922
申请日：1996-12-30
申请人： Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
发明人： Anthony Paul Ingraham , Jaynal Abedin Molla , David Brian Stone
IPC分类号： H01R4/26 , H01R43/02 , H05K3/32 , H01R13/60
CPC分类号： H01R4/26 , H01R12/52 , H05K3/325 , H01R43/02
摘要： A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members. Thereafter, a vacuum is pulled within the sealed chamber, thereby causing the ambient air pressure on the two members to urge the two members toward each other which will embed the dendrites in the dendrite receiving and engaging material to form interconnection therebetween. In order to enhance or improve the bond between the dendrites and the dendrite receiving and securing material, the dendrites and dendrite receiving and securing material each contain a component which can form an intermetallic compound therebetween.
摘要翻译：提供了一种将具有第一面的第一构件与具有第二面的第二构件连接起来利用枝晶的技术。在给定的构造中，树枝状体形成在第一构件的一个面上。树枝状接收和固定材料（优选焊料）形成在第二构件的表面上，其构造基本上确认了在一个面上的树突的给定构型。然后将第一和第二构件相对于彼此放置在第一构件的一个面上的树突与第二构件的表面上的枝晶接收和接合材料接触的位置。然后在围绕树突和树枝状晶体接收和接合材料的第一和第二表面之间提供气密密封，其在第一和第二构件之间形成密封室。此后，在密封室内拉动真空，从而使两个构件上的环境空气压力相互推动两个构件，这两个构件将将树枝状物嵌入枝晶接收和接合材料中以在其间形成互连。为了增强或改善枝晶与树枝状晶体接收和固定材料之间的结合，枝晶和枝晶接收和固定材料各自含有可在其间形成金属间化合物的组分。

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