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1. 发明授权

US5940729A Method of planarizing a curved substrate and resulting structure 失效
公开(公告)号：US5940729A
公开(公告)日：1999-08-17
申请号：US633984
申请日：1996-04-17
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

2. 发明授权

US5939786A Uniform plating of dendrites 失效
标题翻译：树突的均匀电镀
公开(公告)号：US5939786A
公开(公告)日：1999-08-17
申请号：US748462
申请日：1996-11-08
申请人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
IPC分类号： H01L21/48 , H01L23/498 , H05K3/40 , H01L23/48
CPC分类号： H01L23/49811 , H01L21/4853 , H05K3/4007 , H01L2924/0002 , H05K2201/09481 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49155
摘要： The present invention provides uniform dendrites, on circuit features instead of large, elongated dendrites along the edges of the circuit features. The dendrites are formed by a method comprising the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry. The method of the present invention provides uniform dendrites, that is, the dendrites along the edge of the circuitry are within about 50%, preferably about 40%, more preferably within about 25% of the average dendrite height; preferably the dendrites along the edge of the circuitry are within 10% of the highest non-edge dendrite. The invention also relates to electronic structures having uniform dendrites disposed thereon.
摘要翻译：本发明提供了均匀的枝晶，电路特征，而不是沿着电路特征边缘的大的细长的枝晶。树突通过包括以下步骤的方法形成：提供其上设置有电路的基板; 将光致抗蚀剂以优选约为预期枝晶高度的高度的厚度施加到基底上; 成像光致抗蚀剂以暴露电路的顶表面的全部或一部分; 形成枝晶; 并去除光致抗蚀剂。应用用于控制枝晶高度的光致抗蚀剂，使得光致抗蚀剂可以：离开电路的边缘，暴露电路的顶表面; 或邻接电路的边缘并且在电路的顶部边缘上延伸，使得电路的顶部表面的一部分被暴露; 或者不接触电路，也不接触电路底部周围的区域。本发明的方法提供均匀的枝晶，即沿着电路边缘的枝晶在平均枝晶高度的约50％，优选约40％，更优选约25％的范围内; 优选沿着电路边缘的枝晶在最高非边缘枝晶的10％以内。本发明还涉及其上布置有均匀树突的电子结构。

3. 发明授权

US06569604B1 Blind via formation in a photoimageable dielectric material 失效
标题翻译：通过在可光成像的电介质材料中形成盲目
公开(公告)号：US06569604B1
公开(公告)日：2003-05-27
申请号：US09345723
申请日：1999-06-30
申请人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
发明人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
IPC分类号： G03C500
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2224/16 , H05K3/0023 , H05K3/0035 , H05K3/4602 , H05K2201/09827 , H05K2203/1476
摘要： A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.
摘要翻译：盲通孔结构和相关联的激光烧蚀消融方法，其包括在衬底上的可光成像电介质（PID）层内的盲通孔，使得盲通孔的侧壁与盲孔的盲端通过钝角。可以通过依次执行两个过程来形成钝角侧壁。在第一个过程中，通过选择性地暴露在紫外线下的PID层的光成像产生一个或多个具有锐角侧壁的盲孔。光学成像将选择性暴露于紫外线的PID材料交叉连接，使得随后的显影步骤除去未交联或弱交联的PID材料，以同时形成具有不同尺寸开口的多个盲孔。在第二过程中，激光烧蚀被选择性地用于在激光烧蚀的盲孔中形成置换钝角侧壁的方式从特定的盲孔中去除锐角侧壁。或者，可以省略涉及光成像的第一过程，使得涉及激光烧蚀的第二步骤形成整个钝角盲孔。所得到的盲通孔结构包括至少一个具有钝角侧壁的盲孔，并且可选地，至少一个具有锐角侧壁的盲孔。

4. 发明授权

US6150255A Method of planarizing a curved substrate and resulting structure 失效
标题翻译：平面化弯曲基板和结构的方法
公开(公告)号：US6150255A
公开(公告)日：2000-11-21
申请号：US373868
申请日：1999-08-13
申请人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Stephen Joseph Fuerniss , Gary Ray Hill , Anthony Paul Ingraham , Voya Rista Markovich , Jaynal Abedin Molla
IPC分类号： H01L21/60 , H01L23/13 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/00 , H05K3/34 , H05K3/46 , H01L21/44
CPC分类号： H01L23/49833 , H01L23/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05557 , H01L2224/13099 , H01L2224/16225 , H01L2224/2919 , H01L2224/81052 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K1/112 , H05K3/0023 , H05K3/3436 , H05K3/4644
摘要： According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.
摘要翻译：根据本发明，提供了一种用于为平坦化基板提供焊球，特别是多层陶瓷基板的树枝状连接的技术。在衬底在顶表面上具有凸起的中心部分的情况下，其上设置有顶表面冶金衬垫，一层适形的可光成像材料放置在顶表面上。可光成像材料以对应于顶表面冶金垫的图案的图案曝光和显影，以在可光成像材料中形成通孔。将铜镀在与顶部表面冶金垫接触的通孔中。然后将光致变形表面的暴露表面平坦化，优选通过机械抛光以形成平坦的平坦表面，其中通孔的端部暴露。然后，树枝状连接器焊盘在I / C芯片的焊球连接可释放地连接到的通孔的暴露端上生长。

5. 发明授权

US6043150A Method for uniform plating of dendrites 失效
标题翻译：枝晶均匀电镀方法
公开(公告)号：US6043150A
公开(公告)日：2000-03-28
申请号：US304920
申请日：1999-05-04
申请人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Raymond Thomas Galasco , Jaynal Abedin Molla
IPC分类号： H01L21/48 , H01L23/498 , H05K3/40 , H05K3/36
CPC分类号： H01L23/49811 , H01L21/4853 , H05K3/4007 , H01L2924/0002 , H05K2201/09481 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49155
摘要： The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The method comprises the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry. The method of the present invention provides uniform dendrites, that is, the dendrites along the edge of the circuitry are within about 50%, preferably about 40%, more preferably within about 25% of the average dendrite height; preferably the dendrites along the edge of the circuitry are within 10% of the highest non-edge dendrite. The invention also relates to electronic structures having uniform dendrites disposed thereon.
摘要翻译：本发明提供了一种用于形成均匀枝晶的新方法，其电路特征不会导致沿着电路特征边缘的大的细长树突。该方法包括以下步骤：提供其上设置有电路的基板; 将光致抗蚀剂以优选约为预期枝晶高度的高度的厚度施加到基底上; 成像光致抗蚀剂以暴露电路的顶表面的全部或一部分; 形成枝晶; 并去除光致抗蚀剂。应用用于控制枝晶高度的光致抗蚀剂，使得光致抗蚀剂可以：离开电路的边缘，暴露电路的顶表面; 或邻接电路的边缘并且在电路的顶部边缘上延伸，使得电路的顶部表面的一部分被暴露; 或者不接触电路，也不接触电路底部周围的区域。本发明的方法提供均匀的枝晶，即沿着电路边缘的枝晶在平均枝晶高度的约50％，优选约40％，更优选约25％的范围内; 优选沿着电路边缘的枝晶在最高非边缘枝晶的10％以内。本发明还涉及其上布置有均匀树突的电子结构。

6. 发明授权

US5994910A Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips 失效
标题翻译：装置及相应的方法，用于应力测试导线接合型半导体芯片
公开(公告)号：US5994910A
公开(公告)日：1999-11-30
申请号：US160057
申请日：1998-09-24
申请人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
发明人： Francis Joseph Downes, Jr. , Anthony Paul Ingraham , Jaynal Abedin Molla
IPC分类号： G01R31/28 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2862
摘要： An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.
摘要翻译：公开了一种用于应力测试引线接合型半导体芯片的装置和相应的方法。该装置包括夹紧壳体，其中弹簧加载的螺钉延伸穿过壳体的顶端。包含在夹具壳体内的是位于夹具壳体的下端的基本上刚性的电绝缘基板。基板的上表面包括凹陷，其包含由弹性体材料或诸如硅的半导体材料制成的插入件。由例如聚酰亚胺制成的柔性电绝缘层覆盖在基板和插入件上。重要的是，柔性电绝缘层的上表面包括多个树枝状接触。通过这些树突状触点，对引线接合型半导体芯片的接触焊盘进行电接触。

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