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1. 发明申请

US20100301477A1 Silicon-Based Thin Substrate and Packaging Schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US20100301477A1
公开(公告)日：2010-12-02
申请号：US12853711
申请日：2010-08-10
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/498 , H01L23/488
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

2. 发明申请

US20080094093A1 UNIVERSAL ARRAY TYPE PROBE CARD DESIGN FOR SEMICONDUCTOR DEVICE TESTING 有权
标题翻译：通用型阵列探针设计用于半导体器件测试
公开(公告)号：US20080094093A1
公开(公告)日：2008-04-24
申请号：US11551558
申请日：2006-10-20
申请人： Ming-Cheng Hsu , Y. L. Kuo , Pi-Huang Lee , Ann Luh , Frank Hwang , Wen-Hung Wu
发明人： Ming-Cheng Hsu , Y. L. Kuo , Pi-Huang Lee , Ann Luh , Frank Hwang , Wen-Hung Wu
IPC分类号： G01R31/26
CPC分类号： G01R1/07371
摘要： A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.
摘要翻译：用于测试不同半导体器件的通用系统提供具有可用于测试形成在不同半导体器件上的不同测试图案的探针图案的探针头。测试图案的多个凸起或焊盘中的每一个都与探头的相应探头接触，以使半导体器件能够被测试。通用探针头可以附加地或可选地包括在探针头上的衬底设计，其提供探针头的衬底上的图案，其可以与形成在多个不同印刷电路板上的不同图案一起使用，以测试不同的半导体器件。

3. 发明授权

US08248091B2 Universal array type probe card design for semiconductor device testing 有权
标题翻译：用于半导体器件测试的通用阵列型探针卡设计
公开(公告)号：US08248091B2
公开(公告)日：2012-08-21
申请号：US11551558
申请日：2006-10-20
申请人： Hsu Ming Cheng , Yung-Liang Kuo , Pi-Huang Lee , Ann Luh , Frank Hwang , Wen-Hung Wu
发明人： Hsu Ming Cheng , Yung-Liang Kuo , Pi-Huang Lee , Ann Luh , Frank Hwang , Wen-Hung Wu
IPC分类号： G01R31/20 , G01R31/02
CPC分类号： G01R1/07371
摘要： A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.
摘要翻译：用于测试不同半导体器件的通用系统提供具有可用于测试形成在不同半导体器件上的不同测试图案的探针图案的探针头。测试图案的多个凸起或焊盘中的每一个都与探头的相应探头接触，以使半导体器件能够被测试。通用探针头可以附加地或可选地包括在探针头上的衬底设计，其提供探针头的衬底上的图案，其可以与形成在多个不同印刷电路板上的不同图案一起使用，以测试不同的半导体器件。

4. 发明申请

US20080023850A1 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US20080023850A1
公开(公告)日：2008-01-31
申请号：US11493375
申请日：2006-07-26
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装衬底优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。硅基薄封装衬底可以用作半导体芯片的载体。

5. 发明授权

US06920366B1 Heuristics for efficient supply chain planning in a heterogeneous production line 失效
标题翻译：在异质生产线上实现高效供应链计划的启发式
公开(公告)号：US06920366B1
公开(公告)日：2005-07-19
申请号：US10793406
申请日：2004-03-04
申请人： Ann Luh , Shu-Min Chen , Andy Hong , Oliver Wu , Kathy Wang
发明人： Ann Luh , Shu-Min Chen , Andy Hong , Oliver Wu , Kathy Wang
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A computer integrated manufacturing system executes a program process that performs a capacity planning method that allocates usage of a plurality of manufacturing elements of a manufacturing enterprise by major and minor apparatus, squeezing for overhead cost consideration, and site balance for maintain basic operation. The program process begins by receiving at least one fabrication forecast describing scheduling and types of product lots that are predicted to be fabricated within a first period of time by the manufacturing enterprise from at least one order management system of the manufacturing enterprise. Rolling statistics of products lots fabricated during a second period of time are retrieved from a data retention device of the computer integrated manufacturing system. Capacity planning for the allocation of the product lot predicted to be fabricated by the manufacturing elements is performed.
摘要翻译：计算机一体化制造系统执行程序处理，该程序执行通过主要和次要装置分配制造企业的多个制造要素的使用的容量规划方法，挤压间接成本考虑以及用于维持基本操作的场地平衡。程序过程开始于接收至少一个制造预测，描述由制造企业从制造企业的至少一个订单管理系统预测在第一时间段内制造的调度和类型的产品批次。从计算机集成制造系统的数据保持装置检索在第二时间段期间制造的产品批次的滚动统计。执行预期由制造元件制造的产品批次的分配的容量规划。

6. 发明授权

US08174129B2 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US08174129B2
公开(公告)日：2012-05-08
申请号：US12853711
申请日：2010-08-10
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

7. 发明授权

US07804177B2 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US07804177B2
公开(公告)日：2010-09-28
申请号：US11493375
申请日：2006-07-26
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。硅基薄封装衬底可以用作半导体芯片的载体。

8. 发明授权

US08704383B2 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US08704383B2
公开(公告)日：2014-04-22
申请号：US13452562
申请日：2012-04-20
申请人： Szu-Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu-Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

9. 发明申请

US20120199974A1 Silicon-Based Thin Substrate and Packaging Schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US20120199974A1
公开(公告)日：2012-08-09
申请号：US13452562
申请日：2012-04-20
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

10. 发明授权

US06480756B1 Real-time monitor mechanism for heterogeneous production lines 有权
标题翻译：异构生产线的实时监控机制
公开(公告)号：US06480756B1
公开(公告)日：2002-11-12
申请号：US09415230
申请日：1999-10-12
申请人： Hwei-Tsu Ann Luh , Lieh-Chang Tai , Hsin-Ming Hong , Bin-Hong Lin , Min-Huey Tsai
发明人： Hwei-Tsu Ann Luh , Lieh-Chang Tai , Hsin-Ming Hong , Bin-Hong Lin , Min-Huey Tsai
IPC分类号： G06F1900
CPC分类号： G05B19/4183 , G05B2219/31412 , Y02P90/10
摘要： A method for monitoring the real-time production operation is disclosed. The used stage time, the used waiting time, and the theoretical remaining processing time is counted. The allowed stage time, the allowed waiting time, and the allowed slack time is also estimated. The critical stage ratio, the critical waiting ratio, and the critical slack ratio are then calculated by the following equations: critical stage ratio=allowed stage time/used stage time; critical slack ratio=allowed slack time/theoretical remaining processing time; critical waiting ratio=allowed waiting time/used waiting time. Thereafter, the status of the lot in a stage is graded according to its critical ratio of stage, slack, and waiting. Color codes are used to indicate the critical degrees. A stage critical degree report including the WIPs and the color codes is tabled to display all the statuses of the stage.
摘要翻译：公开了一种用于监视实时生产操作的方法。计算使用阶段时间，使用的等待时间和理论剩余处理时间。估计允许的舞台时间，允许的等待时间和允许的松弛时间。关键阶段比例，临界等待比和临界松弛比率，然后通过以下等式计算：临界阶段比=允许阶段时间/使用阶段时间; 临界松弛比=允许松弛时间/理论剩余处理时间; 临时等待比=允许的等待时间/使用的等待时间。此后，一个阶段的批次状况按照阶段，松弛和等待的临界比例进行分级。颜色代码用于指示临界度。提供包括WIP和颜色代码的阶段临界度报告，以显示舞台的所有状态。

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