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1. 发明授权

US08519473B2 Vertical transistor component 有权
标题翻译：垂直晶体管元件
公开(公告)号：US08519473B2
公开(公告)日：2013-08-27
申请号：US12836422
申请日：2010-07-14
申请人： Andreas Peter Meiser , Markus Zundel , Christoph Kadow
发明人： Andreas Peter Meiser , Markus Zundel , Christoph Kadow
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0653 , H01L29/407 , H01L29/41766 , H01L29/41775 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/42392 , H01L29/66666 , H01L29/66734 , H01L29/7397 , H01L29/7827
摘要： A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface.
摘要翻译：通过提供具有第一表面和第二表面的半导体本体产生垂直晶体管组件，在沟槽中产生至少一个栅极接触电极，沟槽从第一表面延伸穿过半导体本体到第二表面，并且在在所述第一表面的区域中连接到所述至少一个栅极接触电极的至少一个栅电极。

2. 发明申请

US20120305987A1 LATERAL TRENCH MESFET 有权
标题翻译：横向梯形管
公开(公告)号：US20120305987A1
公开(公告)日：2012-12-06
申请号：US13152477
申请日：2011-06-03
申请人： Franz Hirler , Andreas Peter Meiser
发明人： Franz Hirler , Andreas Peter Meiser
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/7789 , H01L29/0649 , H01L29/0657 , H01L29/2003
摘要： A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.
摘要翻译：晶体管包括形成在半导体本体中的沟槽，沟槽具有侧壁和底部。晶体管还包括设置在与侧壁相邻的沟槽中的第一半导体材料和设置在沟槽中并与第一半导体材料与侧壁间隔开的第二半导体材料。第二半导体材料具有与第一半导体材料不同的带隙。晶体管还包括设置在沟槽中并且通过第二半导体材料与第一半导体材料间隔开的栅极材料。栅极材料提供晶体管的栅极。源极和漏极区域布置在沟槽中，沟道介于第一或第二半导体材料中的源极和漏极区域之间，使得沟道沿着沟槽的侧壁具有横向电流流动方向。

3. 发明申请

US20120161128A1 DIE PACKAGE 有权
标题翻译： DIE包装
公开(公告)号：US20120161128A1
公开(公告)日：2012-06-28
申请号：US12975448
申请日：2010-12-22
申请人： Stefan Macheiner , Andreas Peter Meiser
发明人： Stefan Macheiner , Andreas Peter Meiser
IPC分类号： H01L23/544
CPC分类号： H01L29/7813 , H01L21/823487 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L27/088 , H01L29/4175 , H01L29/41775 , H01L29/42368 , H01L29/7803 , H01L29/781 , H01L29/7835 , H01L2224/48247 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H02P27/06 , H01L2924/00
摘要： According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements.
摘要翻译：根据一个实施例，提供了一种管芯封装，其包括具有第一多个开关元件的第一管芯结构，其中第一多个开关元件的受控电流输入端子通过公共接触区域电耦合，并且其中受控电流输出端子第一多个开关元件彼此绝缘; 具有第二多个开关元件的第二管芯结构，其中所述第二多个开关元件的受控电流输出端子通过公共接触区域耦合，并且其中所述第二多个开关元件的受控电流输入端子彼此绝缘; 并且其中，对于所述第一多个开关元件中的每一个，所述开关元件的输出端与所述第二多个开关元件中的至少一个开关元件的输入端耦合。

4. 发明申请

US20120133024A1 Semiconductor Device and Method for Manufacturing a Semiconductor Device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20120133024A1
公开(公告)日：2012-05-31
申请号：US12955195
申请日：2010-11-29
申请人： Gerhard Prechtl , Andreas Peter Meiser , Thomas Ostermann
发明人： Gerhard Prechtl , Andreas Peter Meiser , Thomas Ostermann
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331
CPC分类号： H01L29/735 , H01L27/082 , H01L29/1008 , H01L29/6625
摘要： According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.
摘要翻译：根据实施例，提供一种用于制造半导体器件的方法。该方法包括提供掩膜层，其在形成掺杂区域时用作注入掩模，并且当形成开口时形成开口和接触元件时用作蚀刻掩模。接触元件与掺杂区域接触。

5. 发明授权

US08704269B2 Die package 有权
标题翻译：模包
公开(公告)号：US08704269B2
公开(公告)日：2014-04-22
申请号：US12975448
申请日：2010-12-22
申请人： Stefan Macheiner , Andreas Peter Meiser
发明人： Stefan Macheiner , Andreas Peter Meiser
IPC分类号： H01L29/74
CPC分类号： H01L29/7813 , H01L21/823487 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L27/088 , H01L29/4175 , H01L29/41775 , H01L29/42368 , H01L29/7803 , H01L29/781 , H01L29/7835 , H01L2224/48247 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H02P27/06 , H01L2924/00
摘要： According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements.
摘要翻译：根据一个实施例，提供了一种管芯封装，其包括具有第一多个开关元件的第一管芯结构，其中第一多个开关元件的受控电流输入端子通过公共接触区域电耦合，并且其中受控电流输出端子第一多个开关元件彼此绝缘; 具有第二多个开关元件的第二管芯结构，其中所述第二多个开关元件的受控电流输出端子通过公共接触区域耦合，并且其中所述第二多个开关元件的受控电流输入端子彼此绝缘; 并且其中，对于所述第一多个开关元件中的每一个，所述开关元件的输出端与所述第二多个开关元件中的至少一个开关元件的输入端耦合。

6. 发明授权

US08638133B2 Method and circuit for driving an electronic switch 有权
标题翻译：用于驱动电子开关的方法和电路
公开(公告)号：US08638133B2
公开(公告)日：2014-01-28
申请号：US13160809
申请日：2011-06-15
申请人： Steffen Thiele , Andreas Peter Meiser , Franz Hirler
发明人： Steffen Thiele , Andreas Peter Meiser , Franz Hirler
IPC分类号： H03K3/00
CPC分类号： H03K17/0822 , H03K17/14
摘要： Disclosed is an electronic circuit. The electronic circuit includes a transistor having a control terminal to receive a drive signal, and a load path between a first and a second load terminal. A voltage protection circuit is coupled to the transistor, has a control input, is configured to assume one of an activated state and a deactivated state as an operation state dependent on a control signal received at the control input, and is configured to limit a voltage between the load terminals or between one of the load terminals and the control terminal. A control circuit is coupled to the control input of the voltage protection circuit and is configured to deactivate the voltage protection circuit dependent on at least one operation parameter of the transistor and when a voltage across the load path or a load current through the load path is other than zero.
摘要翻译：公开了一种电子电路。电子电路包括具有用于接收驱动信号的控制端子和第一和第二负载端子之间的负载路径的晶体管。电压保护电路耦合到晶体管，具有控制输入，被配置为取决于在控制输入端接收到的控制信号而将激活状态和去激活状态中的一个作为操作状态，并且被配置为限制电压在负载端子之间或负载端子之一和控制端子之间。控制电路耦合到电压保护电路的控制输入，并且被配置为取决于晶体管的至少一个操作参数取消激活电压保护电路，并且当负载路径上的电压或通过负载路径的负载电流为除了零。

7. 发明申请

US20130032855A1 Semiconductor Arrangement 有权
标题翻译：半导体安排
公开(公告)号：US20130032855A1
公开(公告)日：2013-02-07
申请号：US13204347
申请日：2011-08-05
申请人： Stefan Macheiner , Andreas Peter Meiser , Steffen Thiele
发明人： Stefan Macheiner , Andreas Peter Meiser , Steffen Thiele
IPC分类号： H01L29/732 , H01L29/78
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/4903 , H01L2224/49171 , H01L2924/00014 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.
摘要翻译：半导体装置包括第一和第二可控垂直的n沟道半导体芯片。可控制的垂直n沟道半导体芯片中的每一个具有前侧，与前侧相反的后侧，布置在前侧的前侧主触头，布置在后侧的后侧主触头和布置在栅极触点在前侧用于控制前侧主触点和后侧主触点之间的电流。第一和第二半导体芯片的后侧触点彼此电连接。

8. 发明授权

US08368177B2 Integrated circuit with ESD structure 有权
标题翻译：集成电路采用ESD结构
公开(公告)号：US08368177B2
公开(公告)日：2013-02-05
申请号：US12905156
申请日：2010-10-15
申请人： Andreas Peter Meiser , Gerhard Prechtl , Nils Jensen
发明人： Andreas Peter Meiser , Gerhard Prechtl , Nils Jensen
IPC分类号： H01L21/70 , H01L29/66 , H01L29/00 , H01L21/20
CPC分类号： H01L27/0259 , H01L23/60 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone.
摘要翻译：集成电路包括第一导电类型的半导体本体。半导体本体包括与第一导电类型相反的第二导电类型的第一半导体区。第一半导体区延伸到半导体本体的表面。第一导电类型的第二半导体区域嵌入在第一半导体区域中并且延伸到表面的最远处。第二导电类型的第三半导体区域沿着平行于表面的横向方向至少部分地从第一半导体区域突出。接触结构提供与表面上的第一和第二半导体区的电接触。第二半导体区沿着横向布置在从第一半导体区突出的第三半导体区的部分和与第一半导体区接触的接触结构的一部分之间。

9. 发明授权

US09396997B2 Method for producing a semiconductor component with insulated semiconductor mesas 有权
标题翻译：用绝缘半导体台面制造半导体部件的方法
公开(公告)号：US09396997B2
公开(公告)日：2016-07-19
申请号：US13288271
申请日：2011-11-03
申请人： Franz Hirler , Anton Mauder , Hermann Gruber , Hubert Rothleitner , Andreas Peter Meiser
发明人： Franz Hirler , Anton Mauder , Hermann Gruber , Hubert Rothleitner , Andreas Peter Meiser
IPC分类号： H01L21/76 , H01L21/768 , H01L23/48 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78 , H01L21/762 , H01L21/8234 , H01L23/00 , H01L27/088 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/66
CPC分类号： H01L29/407 , H01L21/76224 , H01L21/76898 , H01L21/823481 , H01L23/481 , H01L24/16 , H01L27/088 , H01L29/0653 , H01L29/401 , H01L29/402 , H01L29/408 , H01L29/41741 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/66734 , H01L29/7397 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7813 , H01L2224/16245 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01068 , H01L2924/01074 , H01L2924/12035 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.
摘要翻译：提供一种半导体元件的制造方法。该方法包括：提供具有与第一表面相对的第一表面和第二表面的半导体本体，将绝缘沟槽从第一表面部分地蚀刻到半导体本体中，在绝缘沟槽的一个或多个侧壁上形成第一绝缘层，通过研磨，抛光和CMP工艺中的至少一个来处理第二表面以暴露第一绝缘层，以及在经处理的第二表面上沉积延伸到第一绝缘层的第二绝缘层。

10. 发明授权

US09087829B2 Semiconductor arrangement 有权
标题翻译：半导体安排
公开(公告)号：US09087829B2
公开(公告)日：2015-07-21
申请号：US13204347
申请日：2011-08-05
申请人： Stefan Macheiner , Andreas Peter Meiser , Steffen Thiele
发明人： Stefan Macheiner , Andreas Peter Meiser , Steffen Thiele
IPC分类号： H01L29/66 , H01L23/495 , H01L23/00 , H01L25/07 , H01L23/31
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/4903 , H01L2224/49171 , H01L2924/00014 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.
摘要翻译：半导体装置包括第一和第二可控垂直的n沟道半导体芯片。可控制的垂直n沟道半导体芯片中的每一个具有前侧，与前侧相反的后侧，布置在前侧的前侧主触头，布置在后侧的后侧主触头和布置在栅极触点在前侧用于控制前侧主触点和后侧主触点之间的电流。第一和第二半导体芯片的后侧触点彼此电连接。

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