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1. 外观设计

USD665530S1 Capsule containing washing products 有权
公开(公告)号：USD665530S1
公开(公告)日：2012-08-14
申请号：US29392539
申请日：2011-05-23
申请人： Andreas Gaertner
设计人： Andreas Gaertner

2. 发明授权

US07848153B2 High speed memory architecture 有权
标题翻译：高速内存架构
公开(公告)号：US07848153B2
公开(公告)日：2010-12-07
申请号：US12194414
申请日：2008-08-19
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G11C16/06
CPC分类号： G11C11/4097 , G11C5/025 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.
摘要翻译：公开了存储器件和存储器模块。在一个实施例中，存储器件包括具有第一边缘和与第一边缘相对的第二边缘的半导体衬底。多个存储体设置在半导体衬底的中心部分，每个存储体包括多个存储单元。多个输入/输出触点设置在第一边缘和存储体之间。延迟锁定环电路设置在第一边缘附近。多个地址和命令触点设置在第二边缘和存储体之间。

3. 发明授权

US07829805B2 Shifting device for a motor vehicle 有权
标题翻译：机动车辆换档装置
公开(公告)号：US07829805B2
公开(公告)日：2010-11-09
申请号：US11720005
申请日：2005-11-18
申请人： Metin Ersoy , Andreas Gaertner , Peter Reitz
发明人： Metin Ersoy , Andreas Gaertner , Peter Reitz
IPC分类号： H01H9/06
CPC分类号： H03K17/97 , F16H59/044 , F16H59/105 , F16H2059/0269 , Y10T74/20018
摘要： A shifting device for a motor vehicle is provided with a bracket (3), with a selector lever (7) mounted at the bracket (3) pivotably via a joint (12) and with an angle-measuring device having a signal transmitter (13) and two sensors (14, 15). The angle-measuring device is arranged in the joint (12) and is electrically connected to a control means (19) connected to a motor vehicle transmission (21).
摘要翻译：一种用于机动车辆的移动装置设置有支架（3），其中选择杆（7）经由接头（12）可枢转地安装在支架（3）处，并具有角度测量装置，该角度测量装置具有信号发送器）和两个传感器（14,15）。角度测量装置布置在接头（12）中并且电连接到连接到机动车辆变速器（21）的控制装置（19）。

4. 发明申请

US20060249364A1 Pyrolytic method and apparatus 审中-公开
标题翻译：热解法和仪器
公开(公告)号：US20060249364A1
公开(公告)日：2006-11-09
申请号：US11429753
申请日：2006-05-08
申请人： Andreas Gaertner
发明人： Andreas Gaertner
IPC分类号： C10B29/00 , C10B57/04 , C10B35/00
CPC分类号： B09C1/06 , C10B7/14 , C10B47/46 , C10B53/00
摘要： A method and an apparatus for pyrolytically decomposing carboniferous materials provided with a reactor connected by a carbonization gas conduit to a multiple stage condenser for fractionally recovering pyrolysis oils in a collection container, a central heating element connected to an external heat source, a pre-heating chamber for receiving material after pyrolysis and material prior to pyrolysis for an exchange of heat therebetween, first conveying means for alternatingly moving non-pyrolyzed and pyrolyzed material from the pre-heating chamber into an out of the reactor and second conveying means for moving non-pyrolyzed and pyrolyzed material out of and into the pre-heating chamber. For moving and pyrolyzing the material is preferably retained in basket-like receptacles. The condenser may be connected to the external heat source for utilizing residual carbonization as supplemental heat energy. To render the apparatus moveable, the reactor gas conduit and condenser, the pyrolysis oil collection container, the first and the second conveying means are mounted in separate but connectable container modules.
摘要翻译：热解材料的装料（A）从反应器（1）移动到预热室。待热解的材料的装料（B）放置在室内以通过与电荷（A）的热交换进行预热。放置在反应器中的热解材料的电荷（C）在电荷（A）去除后移动到室中。要热解的材料的电荷（D）通过与电荷（C）进行热交换而放置在室中。将热解的电荷从室中取出，以便从烘箱中进行热解。预加热的电荷从腔室移动到反应器，以便通过电荷（B，D）进行更换。将用于热解的材料的电荷（A）放置在反应器（1）中预定时间。制备待热解的材料的另一种电荷（B）。在预设时间结束时，充电（A）放置在预热室中。通过与电荷（A）的热交换将电荷（B）放入室中进行预热。将热解材料的另一个装料（C）放入反应器中预设时间。制备待热解的材料的另一种电荷（D）。从室中取出电荷（A）。电荷（C）从反应器移动到室中。充电（B）放入反应器预置时间。充电（D）通过与电荷（C）进行热交换而放入室内。将热解的电荷依次从室中取出，以便由烘箱中的热解电荷置换。将预热的电荷从腔室移动到反应器，以便由待热解的材料的电荷进行更换。因此，能够在含有至少一种碳和其它污染物的加热反应器材料中进行热解。对含碳材料的热分解装置包括独立权利要求。

5. 发明授权

US08041865B2 Bus termination system and method 有权
标题翻译：总线终端系统及方法
公开(公告)号：US08041865B2
公开(公告)日：2011-10-18
申请号：US12185472
申请日：2008-08-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
IPC分类号： G06F13/00 , H03K17/16
CPC分类号： G06F13/4086
摘要： A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.
摘要翻译：存储器系统包括耦合到总线的多个集成电路芯片。每个集成电路芯片具有耦合到总线的输入/输出节点，该输入/输出节点具有可编程的片上终端电阻器。通过总线访问集成电路芯片之一的输入/输出节点。每个集成电路芯片的可编程片上终端电阻独立地设置为终端电阻。终端电阻由交易类型和正在被访问的多个存储器件中的哪一个确定，哪些信息可以通过单独的传输控制总线传输。

6. 发明申请

US20100030934A1 Bus Termination System and Method 有权
标题翻译：总线终端系统和方法
公开(公告)号：US20100030934A1
公开(公告)日：2010-02-04
申请号：US12185472
申请日：2008-08-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4086
摘要： A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.
摘要翻译：存储器系统包括耦合到总线的多个集成电路芯片。每个集成电路芯片具有耦合到总线的输入/输出节点，该输入/输出节点具有可编程的片上终端电阻器。通过总线访问集成电路芯片之一的输入/输出节点。每个集成电路芯片的可编程片上终端电阻独立地设置为终端电阻。终端电阻由交易类型和正在被访问的多个存储器件中的哪一个确定，哪些信息可以通过单独的传输控制总线传输。

7. 发明申请

US20100046266A1 High Speed Memory Architecture 有权
标题翻译：高速内存架构
公开(公告)号：US20100046266A1
公开(公告)日：2010-02-25
申请号：US12194414
申请日：2008-08-19
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G11C5/02 , G11C7/00 , G11C8/18 , H01L23/52 , H01L21/00
CPC分类号： G11C11/4097 , G11C5/025 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.
摘要翻译：公开了存储器件和存储器模块。在一个实施例中，存储器件包括具有第一边缘和与第一边缘相对的第二边缘的半导体衬底。多个存储体设置在半导体衬底的中心部分，每个存储体包括多个存储单元。多个输入/输出触点设置在第一边缘和存储体之间。延迟锁定环电路设置在第一边缘附近。多个地址和命令触点设置在第二边缘和存储体之间。

8. 发明申请

US20100032820A1 Stacked Memory Module 审中-公开
标题翻译：堆叠内存模块
公开(公告)号：US20100032820A1
公开(公告)日：2010-02-11
申请号：US12187183
申请日：2008-08-06
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： H01L23/52 , H01L21/00 , H05K7/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/49811 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/18 , H01L2224/0554 , H01L2224/05554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01055 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.
摘要翻译：公开了内存模块，计算系统和制造内存模块的方法。在一个实施例中，存储器模块包括具有与第一侧相对的第一侧和第二侧的衬底。多个引脚设置在基板的第一侧上。第一多个存储器芯片布置在第一芯片层中，第一芯片层覆盖在基板的第二侧。第一多个存储器芯片的电触点电连接到引脚。第二多个存储器芯片被布置在第二芯片层中，第二芯片层覆盖第一芯片层。第二多个存储器芯片的电触点电连接到引脚。

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