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1. 发明授权

US08060550B2 Method and apparatus for integer transformation using a discrete logarithm and modular factorization 失效
标题翻译：使用离散对数和模因式分解的整数变换的方法和装置
公开(公告)号：US08060550B2
公开(公告)日：2011-11-15
申请号：US11535607
申请日：2006-09-27
申请人： Alexandru Fit-Florea , David W. Matula
发明人： Alexandru Fit-Florea , David W. Matula
IPC分类号： G06F1/02 , G06F7/00 , G06F7/38 , G06F15/00
CPC分类号： G06F7/72 , G06F1/0307
摘要： Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.
摘要翻译：转换整数包括接收整数，其中整数可以表示为模数分解。模因式分解包括一个或多个因素，其中每个因子具有指数。整数表示为残差的乘积。从对应于残差乘积的和建立整数的离散对数。从离散对数确定因子指数的值。该整数表示为包含一个或多个因子的模因式分解，其中每个因子具有指数的值。

2. 发明授权

US07962537B2 Determining a table output of a table representing a hierarchical tree for an integer valued function 失效
标题翻译：确定代表整数值函数的分层树的表的表输出
公开(公告)号：US07962537B2
公开(公告)日：2011-06-14
申请号：US11768742
申请日：2007-06-26
申请人： David W. Matula , Mitchell A. Thornton , Alexandru Fit-Florea , Lun Li
发明人： David W. Matula , Mitchell A. Thornton , Alexandru Fit-Florea , Lun Li
IPC分类号： G06F7/00
CPC分类号： G06F1/0353 , G06F2101/10
摘要： Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.
摘要翻译：确定代表整数值函数的层次树的表的表输出包括从表输入确定地址。根据地址选择存储器的子集，其中存储器表示分层树，并且子集表示层次树的子树。从子集中选择位字段，并从位字段中提取位。从提取的比特确定表输出。

3. 发明申请

US20070266068A1 Method And Apparatus For Integer Transformation Using A Discrete Logarithm And Modular Factorization 失效
标题翻译：使用离散对数和模态因式分解的整数变换的方法和装置
公开(公告)号：US20070266068A1
公开(公告)日：2007-11-15
申请号：US11535607
申请日：2006-09-27
申请人： Alexandru Fit-Florea , David Matula
发明人： Alexandru Fit-Florea , David Matula
IPC分类号： G06F1/02 , G06F7/38
CPC分类号： G06F7/72 , G06F1/0307
摘要： Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.
摘要翻译：转换整数包括接收整数，其中整数可以表示为模数分解。模因式分解包括一个或多个因素，其中每个因子具有指数。整数表示为残差的乘积。从对应于残差乘积的和建立整数的离散对数。从离散对数确定因子指数的值。该整数表示为包含一个或多个因子的模因式分解，其中每个因子具有指数的值。

4. 发明授权

US08005884B2 Relaxed remainder constraints with comparison rounding 有权
标题翻译：轻松的剩余约束与比较四舍五入
公开(公告)号：US08005884B2
公开(公告)日：2011-08-23
申请号：US11869426
申请日：2007-10-09
申请人： Alexandru Fit-Florea , Debjit Das-Sarma
发明人： Alexandru Fit-Florea , Debjit Das-Sarma
IPC分类号： G06F7/38
CPC分类号： G06F7/49947
摘要： A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may not be used. Only one quotient may be calculated, rather than two, further reducing needed hardware to perform the rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency is much smaller than a second floating-point multiply accumulate latency.
摘要翻译：计算机系统中有效浮点舍入的系统和方法。计算机系统可以包括用于诸如加法，减法，乘法，除法和平方根之类的浮点算术运算的至少一个浮点单元。对于除法运算，可以放宽剩余部分的限制，以减少查找表的面积。可能不会使用额外的内部精密位。可以仅计算一个商，而不是两个商，进一步减少执行舍入所需的硬件。可能需要比较逻辑，除了余数的计算之外，可以将舍入计算添加几个周期。然而，额外的等待时间远小于第二个浮点乘积累加延迟。

5. 发明申请

US20090094308A1 RELAXED REMAINDER CONSTRAINTS WITH COMPARISON ROUNDING 有权
标题翻译：放松约束的约束
公开(公告)号：US20090094308A1
公开(公告)日：2009-04-09
申请号：US11869426
申请日：2007-10-09
申请人： Alexandru Fit-Florea , Debjit Das-Sarma
发明人： Alexandru Fit-Florea , Debjit Das-Sarma
IPC分类号： G06F7/483
CPC分类号： G06F7/49947
摘要： A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may not be used. Only one quotient may be calculated, rather than two, further reducing needed hardware to perform the rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency is much smaller than a second FMAC latency.
摘要翻译：一种用于计算机系统中有效浮点舍入的系统和方法。计算机系统可以包括用于诸如加法，减法，乘法，除法和平方根之类的浮点算术运算的至少一个浮点单元。对于除法运算，可以放宽剩余部分的限制，以减少查找表的面积。可能不会使用额外的内部精密位。可以仅计算一个商，而不是两个商，进一步减少执行舍入所需的硬件。可能需要比较逻辑，除了余数的计算之外，可以将舍入计算添加几个周期。然而，额外的延迟远远小于第二个FMAC延迟。

6. 发明授权

US08775494B2 System and method for testing whether a result is correctly rounded 有权
标题翻译：用于测试结果是否正确四舍五入的系统和方法
公开(公告)号：US08775494B2
公开(公告)日：2014-07-08
申请号：US13038193
申请日：2011-03-01
申请人： Alexandru Fit-Florea
发明人： Alexandru Fit-Florea
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/4873 , G06F7/49942 , G06F7/5525 , G06F2207/5355 , G06F2207/5356
摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.
摘要翻译：公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

7. 发明申请

US20080005211A1 Determining A Table Output Of A Table Representing A Hierarchical Tree For An Integer Valued Function 失效
标题翻译：确定代表整数值函数的分层树的表的表输出
公开(公告)号：US20080005211A1
公开(公告)日：2008-01-03
申请号：US11768742
申请日：2007-06-26
申请人： David Matula , Mitchell Thornton , Alexandru Fit-Florea , Lun Li
发明人： David Matula , Mitchell Thornton , Alexandru Fit-Florea , Lun Li
IPC分类号： G06F15/00
CPC分类号： G06F1/0353 , G06F2101/10
摘要： Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.
摘要翻译：确定代表整数值函数的层次树的表的表输出包括从表输入确定地址。根据地址选择存储器的子集，其中存储器表示分层树，并且子集表示层次树的子树。从子集中选择位字段，并从位字段中提取位。从提取的比特确定表输出。

8. 发明申请

US20120226730A1 System and Method for Testing Whether a Result is Correctly Rounded 有权
标题翻译：检查结果是否正确四舍五入的系统和方法
公开(公告)号：US20120226730A1
公开(公告)日：2012-09-06
申请号：US13038193
申请日：2011-03-01
申请人： Alexandru FIT-FLOREA
发明人： Alexandru FIT-FLOREA
IPC分类号： G06F7/552 , G06F7/38 , G06F7/44
CPC分类号： G06F7/483 , G06F7/4873 , G06F7/49942 , G06F7/5525 , G06F2207/5355 , G06F2207/5356
摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.
摘要翻译：公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

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