专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06839290B2 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 有权
标题翻译：使用源同步数据选通的高速数据传输的方法，装置和系统
公开(公告)号：US06839290B2
公开(公告)日：2005-01-04
申请号：US10663235
申请日：2003-09-15
申请人： Abid Ahmad , Katen Shah , Alankar Saxena
发明人： Abid Ahmad , Katen Shah , Alankar Saxena
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C11/4093
摘要： According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.
摘要翻译：根据本发明的一个方面，提供了一种方法，其中产生写选通信号以将输出数据锁存到包括一个或多个双数据速率同步动态随机存取存储器（DDR-SDRAM）设备的存储器单元中。写选通信号在与输出数据对应的数据窗口的大致中心处具有边缘转变。使用延迟锁定环（DLL）电路将第一接收时钟信号延迟第一延迟周期以产生第一延迟的接收时钟信号。第一个延迟接收时钟信号用于锁存来自存储器单元的输入数据。

2. 发明授权

US6091431A Method and apparatus for improving processor to graphics device local memory performance 失效
标题翻译：用于提高处理器到图形设备本地存储器性能的方法和装置
公开(公告)号：US6091431A
公开(公告)日：2000-07-18
申请号：US993689
申请日：1997-12-18
申请人： Alankar Saxena , Aditya Sreenvas , Kim A. Meinerth
发明人： Alankar Saxena , Aditya Sreenvas , Kim A. Meinerth
IPC分类号： G06F13/18 , G06F13/16
CPC分类号： G06F13/18
摘要： A graphics device implemented in accordance with one embodiment of the invention includes a first request path to a local memory interface for low-priority read transactions and a second request path to the local memory interface for low-priority write transactions. The second request path is also used for read transactions received over a system bus. The graphics device further includes an arbiter that arbitrates between the first request path and the second request path, with the second request path having a higher priority than the first request path.
摘要翻译：根据本发明的一个实施例实现的图形设备包括到低优先级读取事务的本地存储器接口的第一请求路径以及到低优先级写入事务的本地存储器接口的第二请求路径。第二个请求路径也用于通过系统总线接收的读取事务。所述图形设备还包括仲裁器，所述仲裁器在所述第一请求路径和所述第二请求路径之间进行仲裁，所述第二请求路径具有比所述第一请求路径更高的优先级。

3. 发明授权

US06931484B2 Method and apparatus for handling memory refresh and maintenance operations 有权
标题翻译：用于处理存储器刷新和维护操作的方法和装置
公开(公告)号：US06931484B2
公开(公告)日：2005-08-16
申请号：US10134230
申请日：2002-04-25
申请人： Vasanth Ranganathan , Alankar Saxena
发明人： Vasanth Ranganathan , Alankar Saxena
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1636
摘要： Embodiments of the present invention provide a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications. In particular, refresh and memory operations are executed in two stages. A first stage includes, but is not limited to, memory channel temperature calibration, RAC auto current calibration, and RAC auto temperature calibration. First stage operations are scheduled when the primary display is not requesting data from memory, such as when the display is in its vertical blanking interval. A second stage includes, but is not limited to, memory refreshes and memory current calibration. These operations are scheduled when there are no display streams (primary and secondary) or when display is requesting in a low priority mode.
摘要翻译：本发明的实施例提供了一种用于处理图形和其他应用的存储器刷新和维护操作的方法和装置。特别地，刷新和存储器操作分两个阶段执行。第一阶段包括但不限于内存通道温度校准，RAC自动电流校准和RAC自动温度校准。当主显示器不从存储器请求数据时，例如当显示器处于其垂直消隐间隔时，调度第一阶段操作。第二阶段包括但不限于存储刷新和存储器电流校准。当没有显示流（主要和次要）或显示在低优先级模式下请求时，这些操作将被调度。

4. 发明授权

US06621760B1 Method, apparatus, and system for high speed data transfer using source synchronous data strobe 有权
标题翻译：使用源同步数据选通的高速数据传输的方法，装置和系统
公开(公告)号：US06621760B1
公开(公告)日：2003-09-16
申请号：US09541140
申请日：2000-03-31
申请人： Abid Ahmad , Katen Shah , Alankar Saxena
发明人： Abid Ahmad , Katen Shah , Alankar Saxena
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C11/4093
摘要： According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.
摘要翻译：根据本发明的一个方面，提供了一种方法，其中产生写选通信号以将输出数据锁存到包括一个或多个双数据速率同步动态随机存取存储器（DDR-SDRAM）设备的存储器单元中。写选通信号在与输出数据对应的数据窗口的大致中心处具有边缘转变。使用延迟锁定环（DLL）电路将第一接收时钟信号延迟第一延迟周期以产生第一延迟的接收时钟信号。第一个延迟接收时钟信号用于锁存来自存储器单元的输入数据。

5. 发明授权

US07103730B2 Method, system, and apparatus for reducing power consumption of a memory 有权
标题翻译：用于降低存储器功耗的方法，系统和装置
公开(公告)号：US07103730B2
公开(公告)日：2006-09-05
申请号：US10119864
申请日：2002-04-09
申请人： Alankar Saxena , Aditya Sreenivas
发明人： Alankar Saxena , Aditya Sreenivas
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F12/0215 , G06F12/123 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.
摘要翻译：至少部分地基于活动模式中的行的LRU状态来主动地断言CKE引脚来减少存储器的功耗的方法，系统和装置。

6. 发明授权

US06999091B2 Dual memory channel interleaving for graphics and video 有权
标题翻译：用于图形和视频的双存储器通道交织
公开(公告)号：US06999091B2
公开(公告)日：2006-02-14
申请号：US10033439
申请日：2001-12-28
申请人： Alankar Saxena , Aditya Sreenivas , Tom A. Piazza
发明人： Alankar Saxena , Aditya Sreenivas , Tom A. Piazza
IPC分类号： G06F12/02
CPC分类号： G09G5/39 , G09G2360/122 , G09G2360/125 , H04N19/423 , H04N19/61
摘要： Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.
摘要翻译：本发明的实施例提供了一种用于将平铺的存储器表面最佳地映射到两个存储器通道的方法和装置，以交错的方式操作，使两个通道的存储器效率最大化，同时保持期望的访问粒度。特别地，输入请求地址用于基于瓦片和请求参数来生成用于存储器通道的存储器地址。存储器控制器以这样的格式将该组平铺数据存储在存储器中，使得所选择的拼接数据集合被存储在存储器的交替通道中，使得数据块可以同时访问，而不是依次访问。因此，如果存储器控制器从诸如图形引擎的源接收到数据块，则存储器控制器将存储器中的单个存储器中的数据块的部分存储在存储器中，从而被分割，使得其可经由存储器的备用通道与此同时。

7. 发明授权

US06851069B1 Method, apparatus, and system for high speed data transfer using programmable DLL without using strobes for reads and writes 失效
标题翻译：用于使用可编程DLL进行高速数据传输的方法，装置和系统，而不使用选通信号进行读写
公开(公告)号：US06851069B1
公开(公告)日：2005-02-01
申请号：US09539082
申请日：2000-03-30
申请人： Abid Ahmad , Katen Shah , Alankar Saxena
发明人： Abid Ahmad , Katen Shah , Alankar Saxena
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： G06F13/4243
摘要： According to one aspect of the invention, a method is provided in which a first clock signal is generated. A second clock signal is derived from the first clock signal. The second clock signal is delayed relative to the first clock signal by a first delay period by a delay locked loop (DLL) circuit. The second clock signal is used to latch incoming data from a memory device.
摘要翻译：根据本发明的一个方面，提供了一种产生第一时钟信号的方法。从第一时钟信号导出第二时钟信号。第二时钟信号相对于第一时钟信号通过延迟锁定环（DLL）电路延迟第一延迟周期。第二个时钟信号用于锁存来自存储器件的输入数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式