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1. 发明申请

US20060153776A1 Echogen microparticles essentially used as a contrast agent for ultrasound exploration and/or as emboli for ultrasound detection 审中-公开
标题翻译：回波微粒基本上用作超声波探查的造影剂和/或用于超声检测的栓塞
公开(公告)号：US20060153776A1
公开(公告)日：2006-07-13
申请号：US10543660
申请日：2004-01-28
申请人： Celine Chaix , Nathalie Lassau , Angelo Paci , Pierre Peronneau , Philippe Reb , Alain Roche , Valerie Rouffiac
发明人： Celine Chaix , Nathalie Lassau , Angelo Paci , Pierre Peronneau , Philippe Reb , Alain Roche , Valerie Rouffiac
IPC分类号： A61K49/22
CPC分类号： A61K49/225
摘要： A composition for ultrasonic exploration including echogenic microparticles including a macromolecular network of reticulated hydrophilic polymers and/or copolymers which micro-particles have a diameter between 0.1 μm and 10 μm and are obtained from an inverse mini-emulsion of identical or different monomers or polymers.
摘要翻译：一种用于超声波探伤的组合物，包括回波微粒，其包括网状亲水聚合物和/或共聚物的大分子网络，微粒具有0.1μm和10μm之间的直径，并且由相同或不同单体或聚合物的反相微乳液获得。

2. 发明申请

US20120138715A1 METHOD OF CONTROLLING WOOD PULP PRODUCTION IN A CHIP REFINER 有权
标题翻译：在芯片精炼机中控制木浆生产的方法
公开(公告)号：US20120138715A1
公开(公告)日：2012-06-07
申请号：US13375291
申请日：2010-05-26
申请人： Keith Miles , Lahoucine Ettaleb , Alain Roche
发明人： Keith Miles , Lahoucine Ettaleb , Alain Roche
IPC分类号： D21D1/20
CPC分类号： D21D1/00 , D21D1/002 , D21G9/0018
摘要： A method has been developed that estimates from the on line measurements of readily available process variables the proportion of the mass of fibre in the refining zone of a chip refiner relative to the mass with a full refining zone. This estimate of the filling factor is used to determine the margin available to load the refiner and the control action needed to avoid abnormal operation.
摘要翻译：已经开发了一种方法，其通过在线测量容易获得的工艺变量来估计芯片精磨机的精炼区域中的纤维质量相对于具有完全精炼区域的质量的比例。填充因子的估计用于确定可用于装载精炼机的余量和避免异常操作所需的控制动作。

3. 发明申请

US20060180684A1 Method of refining wood chips or pulp in a high consistency conical disc refiner 有权
标题翻译：在高浓度锥形圆盘磨浆机中精炼木屑或纸浆的方法
公开(公告)号：US20060180684A1
公开(公告)日：2006-08-17
申请号：US11133306
申请日：2005-05-20
申请人： Lahoucine Ettaleb , Alain Roche , Keith Miles
发明人： Lahoucine Ettaleb , Alain Roche , Keith Miles
IPC分类号： D21D1/30
CPC分类号： D21D1/20 , D21D1/002 , D21D1/22 , D21D1/38
摘要： A method is proposed for improving pulp quality at high production rates on conical disc refiners. It permits a reduction in refining intensity by enabling fibre residence time to increase by increasing consistency, while avoiding the problem of plate plugging normally associated with high discharge consistency. In practice, inlet consistency is increased by the in-feed dilution, flat zone dilution or both, but without allowing the discharge consistency to rise. Instead, the discharge consistency is controlled at a fixed optimum value by the addition of dilution water within the conical zone. The result is that residence time is increased, and refining intensity decreased, by raising the consistency in the inner region of the refining zone, while avoiding the plate plugging caused by excessive consistency in the outer region of the refining zone.
摘要翻译：提出了一种在圆锥形精炼机上以高生产率提高纸浆质量的方法。它允许通过使纤维停留时间通过增加一致性而增加，同时避免通常与高排放一致性相关的板堵塞问题，从而降低精炼强度。在实践中，通过进料中稀释，平面区域稀释或两者均可增加入口稠度，但不允许排出稠度上升。相反，通过在锥形区域内添加稀释水将排出稠度控制在固定的最佳值。结果是，通过提高精炼区内部区域的一致性，同时避免由于精炼区外部区域的过度一致性引起的板堵塞，停留时间增加，精炼强度降低。

4. 发明授权

US08590819B2 Method of controlling wood pulp production in a chip refiner 有权
标题翻译：在芯片磨浆机中控制木浆生产的方法
公开(公告)号：US08590819B2
公开(公告)日：2013-11-26
申请号：US13375291
申请日：2010-05-26
申请人： Keith Miles , Lahoucine Ettaleb , Alain Roche
发明人： Keith Miles , Lahoucine Ettaleb , Alain Roche
IPC分类号： B02C1/00 , B02C11/08
CPC分类号： D21D1/00 , D21D1/002 , D21G9/0018
摘要： A method has been developed that estimates from the on line measurements of readily available process variables the proportion of the mass of fiber in the refining zone of a chip refiner relative to the mass with a full refining zone. This estimate of the filling factor is used to determine the margin available to load the refiner and the control action needed to avoid abnormal operation.
摘要翻译：已经开发了一种方法，其通过在线测量容易获得的工艺变量来估计芯片精磨机的精炼区域中的纤维质量相对于具有完全精炼区域的质量的比例。填充因子的估计用于确定可用于装载精炼机的余量和避免异常操作所需的控制动作。

5. 发明授权

US4780429A Method of fabrication of MOS transistors having electrodes of metallic silicide 失效
标题翻译：制造具有金属硅化物电极的MOS晶体管的方法
公开(公告)号：US4780429A
公开(公告)日：1988-10-25
申请号：US10979
申请日：1987-01-12
申请人： Alain Roche , Joseph Borel , Annie Baudrant
发明人： Alain Roche , Joseph Borel , Annie Baudrant
IPC分类号： H01L21/336 , H01L21/60 , H01L21/768 , H01L29/45 , H01L29/49 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/7684 , H01L29/41783 , H01L29/452 , H01L29/4975 , H01L29/4983 , H01L29/66575 , H01L29/66643 , Y10S148/051 , Y10S148/147
摘要： In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.
摘要翻译： PCT No.PCT / FR86 / 00163 Sec。 371日期1987年1月12日 102（e）日期1987年1月12日PCT提交1986年5月13日PCT公布。出版物WO86 / 07190 日期为1986年12月4日。在制造具有非常小尺寸的场效应晶体管的方法中，栅极由第一金属硅化物层形成。沿着栅极的横向边缘形成绝缘堤坝，然后沉积第二层金属硅化物以形成源极和漏极。在第二层覆盖第一层的位置处，通过平坦化蚀刻进行规划，以便产生平坦电极的结构，其中栅极与源电极和漏电极分开的间隔小于在通过光刻分离。

6. 发明授权

US5558724A Method of insulating a magnetic lamination 失效
标题翻译：绝缘层压方法
公开(公告)号：US5558724A
公开(公告)日：1996-09-24
申请号：US526455
申请日：1995-09-11
申请人： Alain Roche
发明人： Alain Roche
IPC分类号： C23C22/18 , C23C22/78 , H01F1/18 , C23F7/10
CPC分类号： H01F1/18 , C23C22/18 , C23C22/78
摘要： A method for making a lamination insulated by iron-manganese phosphate comprises the following operations:1. The lamination is treated with an acid or basic medium to eliminate the surface layer of the lamination that contains excess silicon and aluminum.2. The lamination is rinsed.3. The lamination is brought into contact with a solution of phosphoric acid containing iron phosphate and manganese phosphate for sufficient time to obtain an insulative layer of the required thickness.
摘要翻译：由磷酸铁锰制成的层压方法包括以下操作：1.用酸或碱性介质处理层压，以消除含有多余硅和铝的层压表面层。冲洗层压。 3.使层压与含有磷酸铁和磷酸锰的磷酸溶液接触足够的时间以获得所需厚度的绝缘层。

7. 发明授权

US4844748A Process for the chemical surface treatment of an aluminous product with a view to its phosphating 失效
标题翻译：为了进行磷化处理，可以对铝制品进行化学表面处理
公开(公告)号：US4844748A
公开(公告)日：1989-07-04
申请号：US174294
申请日：1988-03-28
申请人： Jean-Claude Charbonnier , Alain Roche , Maurice Romand , Janine Lenoir , Eric Sahakian
发明人： Jean-Claude Charbonnier , Alain Roche , Maurice Romand , Janine Lenoir , Eric Sahakian
IPC分类号： C23C22/78
CPC分类号： C23C22/78
摘要： This process for treating surfaces of products dip-coated in a bath of molten zinc and aluminum, and intended to be phosphated, involves pickling, preceding the phosphating, with a highly alkaline solution of high pH and containing zinc in solution. The process applies chiefly to products whose coating contains a high proportion of aluminum, particularly in the case of galvanized sheet metal, which it makes easier to phosphate. It is used for painted sheet metal for motor vehicles.
摘要翻译：用于处理浸渍在熔融的锌和铝的浴中，待磷化的产品的表面的该方法包括在磷酸盐之前用高pH的高碱性溶液和在溶液中含有锌的酸洗。该方法主要适用于其涂层中含有较高比例铝的产品，特别是在镀锌金属的情况下，使其更易于磷酸盐化。用于汽车涂漆板材。

8. 发明授权

US4731318A Integrated circuit comprising MOS transistors having electrodes of metallic silicide and a method of fabrication of said circuit 失效
标题翻译：包括具有金属硅化物电极的MOS晶体管和所述电路的制造方法的集成电路
公开(公告)号：US4731318A
公开(公告)日：1988-03-15
申请号：US831851
申请日：1986-02-24
申请人： Alain Roche , Joseph Borel
发明人： Alain Roche , Joseph Borel
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/08 , H01L29/45 , H01L29/49 , G03C5/00 , G03C5/04 , H01L21/00 , B44C1/22
CPC分类号： H01L29/66492 , H01L21/28097 , H01L21/28518 , H01L29/0847 , H01L29/41783 , H01L29/456 , H01L29/4933 , H01L29/66575 , Y10S148/019 , Y10S148/147 , Y10S148/152
摘要： A novel MOS transistor structure comprises electrodes of metallic silicide and especially tantalum silicide. In the case of the gate electrode, the silicide is directly in contact with an insulating thin-film layer. In the case of the drain and source electrodes, the silicide is directly in contact with the monocrystalline silicon. The method of fabrication is thus simplified while avoiding the use of polycrystalline silicon.
摘要翻译：一种新型的MOS晶体管结构包括金属硅化物，特别是硅化钽的电极。在栅电极的情况下，硅化物直接与绝缘薄膜层接触。在漏极和源电极的情况下，硅化物直接与单晶硅接触。因此简化了制造方法，同时避免使用多晶硅。

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