专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06937533B2 Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data 失效
标题翻译：具有半导体存储电路的半导体集成电路具有用于传送地址数据的冗余功能和方法
公开(公告)号：US06937533B2
公开(公告)日：2005-08-30
申请号：US10809308
申请日：2004-03-24
申请人： Takehiko Hojo , Akikuni Sato
发明人： Takehiko Hojo , Akikuni Sato
IPC分类号： G11C29/04 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/802 , G11C29/787 , G11C29/789 , G11C29/812 , G11C2029/1208
摘要： A semiconductor integrated circuit includes a regular cell array, a spare cell array, first and second memory circuits, a determining circuit, a generating circuit and a selecting circuit. When the regular cell array contains a defective regular memory cell, the defective regular memory cell is replaced with a spare memory cell in the spare cell array. Each of the first memory circuits stores data indicating whether an associated spare memory cell is used or not. Any of the second memory circuits stores address data indicating the address of the defective regular memory cell. The determining circuit determines whether each of the spare memory cells is used or not, based on the data stored in an associated first memory circuit. The generating circuit generates predetermined data. The selecting circuit selects and outputs the data generated by the generating circuit or address data stored in each of the second memory circuits.
摘要翻译：半导体集成电路包括常规单元阵列，备用单元阵列，第一和第二存储器电路，确定电路，发生电路和选择电路。当常规单元阵列包含有缺陷的常规存储单元时，缺陷常规存储单元被备用单元阵列中的备用存储单元替代。每个第一存储器电路存储指示是否使用相关联的备用存储单元的数据。第二存储器电路中的任何一个存储指示缺陷常规存储器单元的地址的地址数据。基于存储在关联的第一存储器电路中的数据，确定电路确定每个备用存储单元是否被使用。发电电路产生预定的数据。选择电路选择并输出由发生电路产生的数据或存储在每个第二存储器电路中的地址数据。

2. 发明申请

US20080284494A1 FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA 审中-公开
标题翻译：保险丝装置，用于写入数据的方法，读取数据的方法以及用于写入和读取数据的方法
公开(公告)号：US20080284494A1
公开(公告)日：2008-11-20
申请号：US12118033
申请日：2008-05-09
申请人： Hideaki Yamauchi , Akikuni Sato , Takehiko Hojo
发明人： Hideaki Yamauchi , Akikuni Sato , Takehiko Hojo
IPC分类号： H01H37/76
CPC分类号： H01L27/101 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively.
摘要翻译：保险丝装置包括多个串联连接的熔丝元件，其数量为n（n为2以上的整数），连接到作为n个串联连接的熔丝元件的顶部的第一熔丝元件的一端的电源，和多个程序控制晶体管。每个编程控制晶体管分别连接到熔丝元件之间的每个节点，并分别连接到第n个熔丝元件的端部。

3. 发明申请

US20050122799A1 SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SEMICONDUCTOR MEMORY CIRCUIT HAVING REDUNDANCY FUNCTION AND METHOD FOR TRANSFERRING ADDRESS DATA 失效
标题翻译：具有冗余功能的半导体存储器电路提供的半导体集成电路和用于传送地址数据的方法
公开(公告)号：US20050122799A1
公开(公告)日：2005-06-09
申请号：US10809308
申请日：2004-03-24
申请人： Takehiko Hojo , Akikuni Sato
发明人： Takehiko Hojo , Akikuni Sato
IPC分类号： G11C29/04 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/802 , G11C29/787 , G11C29/789 , G11C29/812 , G11C2029/1208
摘要： A semiconductor integrated circuit includes a regular cell array, a spare cell array, first and second memory circuits, a determining circuit, a generating circuit and a selecting circuit. When the regular cell array contains a defective regular memory cell, the defective regular memory cell is replaced with a spare memory cell in the spare cell array. Each of the first memory circuits stores data indicating whether an associated spare memory cell is used or not. Any of the second memory circuits stores address data indicating the address of the defective regular memory cell. The determining circuit determines whether each of the spare memory cells is used or not, based on the data stored in an associated first memory circuit. The generating circuit generates predetermined data. The selecting circuit selects and outputs the data generated by the generating circuit or address data stored in each of the second memory circuits.
摘要翻译：半导体集成电路包括常规单元阵列，备用单元阵列，第一和第二存储器电路，确定电路，发电电路和选择电路。当常规单元阵列包含有缺陷的常规存储单元时，缺陷常规存储单元被备用单元阵列中的备用存储单元替代。每个第一存储器电路存储指示是否使用相关联的备用存储单元的数据。第二存储器电路中的任何一个存储指示缺陷常规存储器单元的地址的地址数据。基于存储在关联的第一存储器电路中的数据，确定电路确定每个备用存储单元是否被使用。发电电路产生预定的数据。选择电路选择并输出由发生电路产生的数据或存储在每个第二存储器电路中的地址数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式