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1. 发明申请

US20110133773A1 High Performance Output Drivers and Anti-Reflection Circuits 审中-公开
标题翻译：高性能输出驱动器和反反射电路
公开(公告)号：US20110133773A1
公开(公告)日：2011-06-09
申请号：US12772143
申请日：2010-04-30
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/0005 , H03K19/01721 , H03K19/0941 , H04L25/0278
摘要： Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
摘要翻译：通过使用n沟道晶体管作为上拉晶体管和/或p沟道晶体管作为高性能输出驱动器的下拉晶体管来解决已知输出驱动器的长期存在的性能，噪声和功耗问题。片上终端电路分支为连接到同一传输线的多个芯片提供有效的防反射功能。

2. 发明申请

US20100327902A1 Power saving termination circuits for dram modules 审中-公开
标题翻译：电池模块的节能终端电路
公开(公告)号：US20100327902A1
公开(公告)日：2010-12-30
申请号：US12456947
申请日：2009-06-25
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K17/16 , H01L21/20
CPC分类号： H03K19/0005 , G11C7/1048 , G11C7/1066 , G11C11/4093 , H01L27/10897 , H01L28/20 , H01L28/40 , H03K19/0013
摘要： The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces.
摘要翻译：本发明通过用终端电阻器替代用于支持具有RC终端电路的SSTL DRAM接口来提供节能方法; RC终端电路相对于现有技术的低频终端电阻消耗的功率明显较低，并且在高频下表现为匹配阻抗。类似的方法和结构也适用于PCIe，SATA或MIPI差分接口。

3. 发明申请

US20090103372A1 HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS 审中-公开
公开(公告)号：US20090103372A1
公开(公告)日：2009-04-23
申请号：US11933556
申请日：2007-11-01
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C7/10 , G06F1/16 , H01S4/00
CPC分类号： G06F13/4243 , Y10T29/49002
摘要： The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

4. 发明申请

US20090103387A1 HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS 审中-公开
标题翻译：高性能高容量存储系统
公开(公告)号：US20090103387A1
公开(公告)日：2009-04-23
申请号：US11874914
申请日：2007-10-19
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C8/00 , H05K3/00
CPC分类号： G11C5/063 , G11C5/04 , Y10T29/49124
摘要： The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.
摘要翻译：本发明提供了开发用于增加存储器系统容量的存储器系统架构。通常应用程序包括计算机的主内存。本发明的存储器系统可以通过一个或两个量级的量级来实现比现有技术系统更大的容量，而不会在没有或最小的修改的情况下使用与现有存储器系统兼容的系统接口，而性能没有显着的降低。

5. 发明申请

US20030053330A1 Dual capacitor dynamic random access memory cell 审中-公开
标题翻译：双电容动态随机存取存储单元
公开(公告)号：US20030053330A1
公开(公告)日：2003-03-20
申请号：US10167383
申请日：2002-06-10
申请人： UniRAM Technology, Inc.
发明人： Jeng-Jye Shau , Byeong-Cheal Na
IPC分类号： G11C011/24
CPC分类号： G11C11/405
摘要： This invention discloses a dynamic random access memory (DRAM) memory cell. The DRAM memory cell includes a first transistor-capacitor circuit connected to a first bitline BL and a second transistor-capacitor circuit connected to a second bitline BLnull. The memory cell further includes a gate of the first transistor connected to a gate of the second transistor. The DRAM cell further includes a sense amplifier connected to the first bit line BL and the second bit line BLnull for measuring a binary bit from sensing a voltage difference between the first and second transistor-capacitor circuits independent from a pre-charged bit-line voltage.
摘要翻译：本发明公开了一种动态随机存取存储器（DRAM）存储单元。 DRAM存储单元包括连接到第一位线BL的第一晶体管 - 电容器电路和连接到第二位线BL＃的第二晶体管 - 电容器电路。存储单元还包括连接到第二晶体管的栅极的第一晶体管的栅极。 DRAM单元还包括连接到第一位线BL的读出放大器和用于测量二进制位的第二位线BL＃，以检测第一和第二晶体管 - 电容器电路之间的电压差，而不依赖于预充电位线电压。

6. 发明申请

US20030043657A1 High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines 失效
标题翻译：具有多维度一级位线的高性能嵌入式半导体存储器件
公开(公告)号：US20030043657A1
公开(公告)日：2003-03-06
申请号：US10269571
申请日：2002-10-10
申请人： UniRAM Technology, Inc.
发明人： Jeng-Jye Shau
IPC分类号： G11C007/00
CPC分类号： G11C7/1006 , G11C7/18 , G11C8/12 , G11C11/406 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L27/10829 , H01L27/10897
摘要： A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.
摘要翻译：动态随机存取存储器使用多维位线结构解决了长期存在的紧密间距布局问题。解码器设计的改进进一步减少了该存储器的总面积。新颖的存储器访问过程提供使内部存储器刷新对于外部用户完全不可见的能力。通过使用这种存储器架构，可以实现更高性能的DRAM而不降低存储器密度。系统支持的要求也大大简化。

7. 发明申请

US20020039317A1 High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines 失效
标题翻译：具有多维一级位线的高性能可擦除可编程只读存储器（EPROM）器件
公开(公告)号：US20020039317A1
公开(公告)日：2002-04-04
申请号：US09860215
申请日：2001-05-18
申请人： UniRAM Technology, Inc.
发明人： Jeng-Jye Shau
IPC分类号： G11C007/00
CPC分类号： G11C7/1006 , G11C7/18 , G11C8/12 , G11C11/406 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L27/10829 , H01L27/10897
摘要： A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction. The EPROM memory device further includes a plurality of word lines intersected with the first-direction first-level bit lines. The EPROM memory cell array further includes a plurality of EPROM memory cells wherein each of the plurality of memory cells being coupled between one of the first-direction first level bit lines and one of the word lines for storing data therein. And, the EPROM memory device further includes a plurality of different-direction first level bit-lines disposed along at least one different direction different from the first direction. Each of the different-direction first-level bit lines connected between a plurality of the first-direction first level bit lines and one of the first level sense-circuits.
摘要翻译：提供用于与多个第一级感测电路一起操作的半导体可擦除可编程只读存储器（EPROM）器件。 EPROM存储器件包括具有沿着第一方向平行布置的多个第一方向第一级位线的EPROM存储单元阵列。 EPROM存储器件还包括与第一方向第一级位线相交的多个字线。 EPROM存储单元阵列还包括多个EPROM存储器单元，其中多个存储单元中的每一个耦合在第一方向第一电平位线之一和用于在其中存储数据的一条字线之间。并且，EPROM存储装置还包括沿着与第一方向不同的至少一个不同方向布置的多个不同方向的第一级位线。连接在多个第一方向第一电平位线和第一电平检测电路中的一个之间的不同方向的第一电平位线中的每一个。

8. 发明申请

US20110089555A1 AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS 有权
标题翻译：面积安装套件面积减少
公开(公告)号：US20110089555A1
公开(公告)日：2011-04-21
申请号：US12686551
申请日：2010-01-13
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H01L23/48 , H01L23/12 , H01L21/60
CPC分类号： H01L23/48 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/072 , H01L27/0255 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , Y10T29/49121 , Y10T29/49147 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
摘要翻译：使用由侧壁绝缘体绝缘的侧壁导体引线形成用于在硅衬底上制造的有源电路的封装级导体引线，本发明的优选实施例显着地减少了表面贴装封装芯片的面积。除了减少面积之外，这些方法还显着降低了成本并降低了寄生阻抗。

9. 发明申请

US20100237904A1 High Performance Output Drivers and Anti-Reflection Circuits 审中-公开
标题翻译：高性能输出驱动器和反反射电路
公开(公告)号：US20100237904A1
公开(公告)日：2010-09-23
申请号：US12795005
申请日：2010-06-07
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K19/003 , H03K3/00
CPC分类号： H03K19/018585 , H04L25/0264 , H04L25/0272 , H04L25/028
摘要： Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
摘要翻译：通过使用n沟道晶体管作为上拉晶体管和/或p沟道晶体管作为高性能输出驱动器的下拉晶体管来解决已知输出驱动器的长期存在的性能，噪声和功耗问题。片上终端电路分支为连接到同一传输线的多个芯片提供有效的防反射功能。

10. 发明申请

US20090103373A1 HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS 审中-公开
公开(公告)号：US20090103373A1
公开(公告)日：2009-04-23
申请号：US12039680
申请日：2008-02-28
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

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