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    • 6. 发明授权
    • Image reading apparatus and method of controlling the same
    • 图像读取装置及其控制方法
    • US08169674B2
    • 2012-05-01
    • US12104654
    • 2008-04-17
    • Young Min Kim
    • Young Min Kim
    • H04N1/46
    • H04N1/00795H04N1/00814H04N1/00832H04N1/0464H04N1/12H04N1/193H04N1/2032H04N2201/0081H04N2201/0098
    • An image reading apparatus capable of changing a main reading unit at an appropriate time point such that a plurality of reading units can be equally used, and a method of controlling the same. The image reading apparatus includes an automatic document feeder, a first reading unit to read a first side of a document fed by the automatic document feeder and to function as a main reading unit, a second reading unit to read a second side of the document fed by the automatic document feeder; and a control unit to change the main reading unit from the first reading unit to the second reading unit if the number of times La of usage of the first reading unit reaches a reference value. The control unit compares the number of times La of usage of the first reading unit with a predicted lifetime Lt of the first reading unit and changes the main reading unit to the second reading unit if it is determined that the number of times La of usage of the first reading unit reaches a predetermined percentage of the predicted lifetime of the first reading unit. The control unit determines whether the main reading unit is changed or not, based on frequencies of use of the first reading unit and the second reading unit.
    • 一种能够在适当的时间点改变主读取单元以使得可以平等地使用多个读取单元的图像读取装置及其控制方法。 图像读取装置包括自动送稿器,第一读取单元,用于读取由自动送稿器馈送并用作主读取单元的原稿的第一面,第二读取单元,用于读取馈送的原稿的第二面 由自动送纸器; 以及控制单元,如果第一读取单元的使用次数La达到参考值,则将主读取单元从第一读取单元改变为第二读取单元。 控制单元将第一读取单元的使用次数La与第一读取单元的预测寿命Lt进行比较,并且如果确定使用的次数La,则将主读取单元改变为第二读取单元 第一读取单元达到第一读取单元的预测寿命的预定百分比。 控制单元基于第一读取单元和第二读取单元的使用频率来确定主读取单元是否改变。
    • 8. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US07312117B2
    • 2007-12-25
    • US11193788
    • 2005-07-28
    • Doo-Young LeeYoo-Chul KongJong-Chul ParkSang-Sup Jeong
    • Doo-Young LeeYoo-Chul KongJong-Chul ParkSang-Sup Jeong
    • H01L21/8242
    • H01L28/91H01L21/76838H01L27/10814H01L27/10855H01L27/10885
    • A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.
    • 半导体器件包括在限定在衬底上的有源区上沿第一方向延伸的字线结构。 第一和第二接触垫形成在字线结构两侧的有源区上。 位线结构电连接到第一接触焊盘并沿基本垂直于第一方向的第二方向延伸。 在具有位线结构的基板上形成绝缘层结构。 存储节点接触插头通过绝缘层结构电连接到第二接触垫。 作为电容器的一部分的存储节点电极形成在存储节点接触插头上。 存储节点接触插头具有下部和具有比下部的宽度宽的上部,其垂直方向垂直于第一和第二方向。
    • 10. 发明授权
    • Double data rate synchronous dynamic random access memory semiconductor device
    • 双数据速率同步动态随机存取存储器半导体器件
    • US07038972B2
    • 2006-05-02
    • US10793209
    • 2004-03-04
    • Sung-min SeoChi-wook KimKyu-hyoun Kim
    • Sung-min SeoChi-wook KimKyu-hyoun Kim
    • G01C8/00
    • G11C7/1066G11C7/1051G11C7/1072G11C7/1078G11C7/1093G11C7/222
    • A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.
    • 提供了一种双倍数据速率(“DDR”)同步动态随机存取存储器(“SDRAM”)半导体器件,其防止当将数据写入DDR SDRAM半导体器件时从数据读取和写入DDR SDRAM半导体器件的数据之间的冲突 ,其包括延迟锁定环(“DLL”)电路,时钟信号控制单元,输出单元和输出控制单元,其中DLL电路补偿输入时钟信号的偏斜并产生输出时钟信号; 当读出存储在DDR SDRAM半导体器件中的数据时,时钟信号控制单元接收到激活的读取信号,当DLL电路对输入时钟信号执行锁定操作时激活的DLL锁定信号和输出时钟信号,并且输出 当读取信号或DLL锁定信号有效时,输出时钟信号; 输出单元缓冲存储在DDR SDRAM半导体器件中的数据,并将数据与从时钟信号控制单元输出的输出时钟信号同步地输出到DDR SDRAM半导体器件的外部; 并且输出控制单元接收从时钟信号控制单元输出的输出时钟信号和读取信号,并将读出的信号与从时钟信号控制单元输出的输出时钟信号同步输出到输出单元。