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    • 3. 发明授权
    • NFC “split stack” architecture
    • US10243619B2
    • 2019-03-26
    • US15769652
    • 2016-10-18
    • PANTHRONICS AG
    • Michael PieberTomaz FelicijanJakob Jongsma
    • H04B5/00H04W4/80H04L29/06H04L29/08
    • A device (5; 16; 26) that processes a Near Field Communication type application which device (5; 16; 26) comprises: a host controller circuit (3; 27) that processes device applications, that use the Near Field Communication type application, and that processes a host driver (7; 28) that communicates based on a first interface protocol (NCI; EMV); a NFC controller circuit (4; 33) that processes a Near Field Communication type contactless interface (6; 35) and a controller driver (11; 32) that interfaces with the host controller circuit (3; 27), wherein the host controller circuit (3; 27) processes a first transmission module (9; 30) that interfaces with the host driver (7; 28) based on the first interface protocol (NCI; EMV) and with the controller driver (11; 32) based on a second interface protocol, which first transmission module (9; 30) furthermore processes substantially all none-time critical and/or memory consuming tasks of the Near Field Communication type application and wherein the NFC controller circuit (4; 33) comprises a second transmission module (12, 34) that processes all time critical tasks for the Near Field Communication type application towards the Near Field Communication type contactless interface (6; 35).
    • 5. 发明申请
    • TARGET DETECTION BY RFID READER
    • US20190020378A1
    • 2019-01-17
    • US16065912
    • 2016-12-12
    • PANTHRONICS AG
    • Michael PIEBERJakob JONGSMA
    • H04B5/00G06K7/10G06K7/00
    • A reader (5) with an antenna (6) that transmits a HF field (10) with a carrier frequency and receives an analog input signal (11) with the antenna (6), which analog input signal (11) may be load modulated with a modulation frequency, and outputs digital data detected in the input signal (11), which reader (5) comprises: a mixer (13, 15) that mixes the input signal (11) with a carrier frequency signal (9, 16) and provides a mixed output signal (14); target detection means (22) to detect the presence of a target in the HF field (10) and to activate processing of the input signal (11) to communicate with the target, wherein target detection means (22) comprise: low-pass filter means (23, 25) to eliminate signal components of the mixed output signal (14) at the modulation frequency and above and to provide a filtered output signal (24); quantification means (32) that quantify the filtered output signal (24) and provide quantified detection data (33); decision means (36) that compare the quantified detection data (33) with a threshold (37) to provide a target detected information (38), while the threshold (37) is set in-between quantified detection data (33) received with and without a target present in the HF field (10).
    • 8. 发明申请
    • RECEIVER TO PROCESS A LOAD MODULATED ANALOG INPUT SIGNAL
    • US20180331867A1
    • 2018-11-15
    • US15775314
    • 2016-11-04
    • PANTHRONICS AG
    • Jakob JONGSMA
    • H04L27/22
    • H04L27/22G06K7/0008H04B1/30
    • A Receiver (17) that receives a load modulated analog input signal (19) and outputs digital data (20) detected in the input signal (19), which receiver (17) comprises: an in-phase mixer (21) that mixes the input signal (19) with an in-phase carrier frequency (22) and provides an in-phase component (23) of the down-converted input signal and a quadrature-phase mixer (24) that mixes the input signal (19) with a quadrature-phase carrier frequency (25) and provides a quadrature-phase component (26) of the down-converted input signal; an amplifier (29, 30) to amplify the in-phase component (23) and the quadrature-phase component (26) of the down-converted input signal; a DC block filter (31) to remove the DC component of the in-phase component (23) and the quadrature-phase component (26), wherein the receiver furthermore comprises: an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in-phase component (23) and the quadrature-phase component (26) to correlate the in-phase component (23) and the quadrature-component (26) with an in-phase component (37) and a quadrature-phase component (38) of a subcarrier or code clock frequency of the input signal (19); a combiner (41) to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer (43) to sample an output signal (42) of the combiner (41) at maximum energy levels to output the digital data (20) detected in the input signal (19).