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1. 发明申请

US20070069241A1 Memory with high dielectric constant antifuses and method for using at low voltage 审中-公开
标题翻译：高介电常数反熔丝的存储器和低电压使用的方法
公开(公告)号：US20070069241A1
公开(公告)日：2007-03-29
申请号：US11173973
申请日：2005-07-01
申请人： Xiaoyu Yang , Roy Scheuerlein , Feng Li , Albert Meeks
发明人： Xiaoyu Yang , Roy Scheuerlein , Feng Li , Albert Meeks
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L45/12 , G11C17/00 , G11C17/16 , H01L23/5252 , H01L27/101 , H01L45/04 , H01L45/146 , H01L2924/0002 , H01L2924/00
摘要： A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.
摘要翻译：通过使用具有比二氧化硅更高的介电常数和更高的加速因子的反熔丝材料，并且通过使用具有比硅更低的带隙的二极管，可以使具有包括二极管和反熔丝的存储单元的存储器阵列更小并且在较低的电压下编程。这样的存储器阵列可以通过使用高加速因子和较低带隙材料而具有长的工作寿命。具有介于5和27之间的介电常数的防腐材料，例如铪硅氮氧化物或氧化铪铪是特别有效的。带隙低于硅的二极管材料，例如锗或硅 - 锗合金是特别有效的。

2. 发明申请

US20060285422A1 Floating body memory cell system and method of manufacture 有权
公开(公告)号：US20060285422A1
公开(公告)日：2006-12-21
申请号：US11157293
申请日：2005-06-20
申请人： Roy Scheuerlein
发明人： Roy Scheuerlein
IPC分类号： G11C8/00
CPC分类号： H01L27/1203 , G11C11/404 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/12 , H01L29/7841
摘要： A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

3. 发明申请

US20060273298A1 Rewriteable memory cell comprising a transistor and resistance-switching material in series 审中-公开
标题翻译：包括晶体管和电阻切换材料的可重写存储单元
公开(公告)号：US20060273298A1
公开(公告)日：2006-12-07
申请号：US11143269
申请日：2005-06-02
申请人： Christopher Petti
发明人： Christopher Petti
IPC分类号： H01L29/06
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance-switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have either a vertically oriented channel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.
摘要翻译：提供一种非易失性存储单元，该单元包括与电阻切换材料串联的晶体管，其可以在至少两个稳定的电阻状态（例如高电阻状态和低电阻状态）之间切换。在优选实施例中，晶体管是TFT，其具有未形成在单晶晶片衬底中的沟道区。在优选实施例中，晶体管可以具有垂直定向的通道或横向定向的通道。任何一个实施例可以形成在单片三维存储器阵列中，其中可以在单个衬底上方形成多个存储器级，形成高密度非易失性存储器阵列。

4. 发明申请

US20060216931A1 Method for reducing dielectric overetch when making contact to conductive features 有权
公开(公告)号：US20060216931A1
公开(公告)日：2006-09-28
申请号：US11089771
申请日：2005-03-25
申请人： Christopher Petti
发明人： Christopher Petti
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

5. 发明申请

US20060157679A1 Structure and method for biasing phase change memory array for reliable writing 有权
公开(公告)号：US20060157679A1
公开(公告)日：2006-07-20
申请号：US11040262
申请日：2005-01-19
申请人： Roy Scheuerlein
发明人： Roy Scheuerlein
IPC分类号： H01L29/02
CPC分类号： G11C11/21 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481
摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

6. 发明申请

US20060087005A1 Deposited semiconductor structure to minimize N-type dopant diffusion and method of making 有权
标题翻译：沉积的半导体结构使N型掺杂剂扩散最小化和制备方法
公开(公告)号：US20060087005A1
公开(公告)日：2006-04-27
申请号：US11298331
申请日：2005-12-09
申请人： S. Herner
发明人： S. Herner
IPC分类号： H01L31/117 , H01L29/00
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.
摘要翻译：在沉积的硅中，诸如磷和砷的n型掺杂剂倾向于寻求硅的表面，随着层的沉积而上升。当在没有提供n型掺杂剂的n掺杂硅上沉积第二未掺杂或p掺杂的硅层时，该第二硅层的第一厚度倾向于包括从较低水平扩散的不期望的n型掺杂剂。当锗与硅合金化时，这种表面寻找行为减弱。在一些设备中，对于第二层可能不是有利的具有显着的锗含量。在本发明中，沉积第一重n掺杂半导体层（优选至少10原子％的锗），随后是几乎没有或没有n型掺杂剂的硅 - 锗覆盖层，随后是几乎没有或没有 n型掺杂剂和少于10at％的锗。第一层和覆盖层中的锗使n型掺杂剂的扩散最小化到上述的锗贫层中。

7. 发明申请

US20060083069A1 System and method of controlling a three-dimensional memory 有权
标题翻译：控制三维存储器的系统和方法
公开(公告)号：US20060083069A1
公开(公告)日：2006-04-20
申请号：US10955048
申请日：2004-09-30
申请人： Luca Fasoli
发明人： Luca Fasoli
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0466 , G11C16/12 , G11C16/3481
摘要： A system and method of controlling a three dimensional memory is disclosed. In a particular embodiment, the system is implemented as an integrated circuit including a microcontroller having a control signal output, a three-dimensional monolithic non-volatile memory having a plurality of levels of memory cells above a silicon substrate and having an input responsive to the control signal output, a counter coupled to the microcontroller, and a program memory. The counter is to step through a series of time steps defining a program pulse time interval of a first program pulse to be applied to at least one selected memory cell within the three-dimensional monolithic non-volatile memory. The program memory is accessible to the microcontroller, and the program memory includes a sequence of program instructions corresponding to a memory operation with respect to the three-dimensional monolithic non-volatile memory.
摘要翻译：公开了一种控制三维存储器的系统和方法。在特定实施例中，该系统被实现为包括具有控制信号输出的微控制器的集成电路，具有在硅衬底上方的多个级别的存储器单元的三维单片非易失性存储器，并具有响应于控制信号输出，耦合到微控制器的计数器和程序存储器。计数器是通过一系列时间步骤来定义要应用于三维单片非易失性存储器内的至少一个所选存储单元的第一编程脉冲的编程脉冲时间间隔。程序存储器可由微控制器访问，并且程序存储器包括与相对于三维单片非易失性存储器的存储器操作相对应的程序指令序列。

8. 发明申请

US20060073657A1 Junction diode comprising varying semiconductor compositions 有权
标题翻译：结二极管包括不同的半导体组成
公开(公告)号：US20060073657A1
公开(公告)日：2006-04-06
申请号：US10954577
申请日：2004-09-29
申请人： S. Herner , Andrew Walker
发明人： S. Herner , Andrew Walker
IPC分类号： H01L21/8234 , H01L21/8222 , H01L21/82
CPC分类号： H01L27/1021 , H01L27/24
摘要： The invention provides for a junction diode including a heavily doped first region having a first conductivity type, a second lightly doped or intrinsic region having a second conductivity type, and a third heavily doped region having a second conductivity type. The junction diode comprises more than one semiconductor or semiconductor alloy. In preferred embodiments, the lightly doped or intrinsic region has a higher proportion of germanium than on or the other or both of the heavily doped regions. In preferred embodiments, the junction diode is vertically oriented, and the top region has a higher proportion of silicon than the other regions.
摘要翻译：本发明提供一种结二极管，其包括具有第一导电类型的重掺杂第一区，具有第二导电类型的第二轻掺杂或本征区，以及具有第二导电类型的第三重掺杂区。结二极管包括多于一个的半导体或半导体合金。在优选实施例中，轻掺杂或本征区域具有比重掺杂区域上或其他或两者上更高比例的锗。在优选实施例中，结二极管是垂直取向的，并且顶部区域具有比其它区域更高比例的硅。

9. 发明授权

US07022572B2 Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells 有权
标题翻译：具有无源元件存储单元无扰编程的集成电路的制造方法
公开(公告)号：US07022572B2
公开(公告)日：2006-04-04
申请号：US10994020
申请日：2004-11-19
申请人： Roy E. Scheuerlein , N. Johan Knall
发明人： Roy E. Scheuerlein , N. Johan Knall
IPC分类号： H01L21/336
CPC分类号： G11C13/0014 , B82Y10/00 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72
摘要： In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
摘要翻译：在无源元件存储器阵列中，例如沿着阵列线中的一个或两个具有连续半导体区域的轨道堆叠阵列，对存储器单元的编程可能由于沿着阵列线从所选择的单元的泄漏路径而扰乱附近的存储器单元到相邻的单元格。即使电压不变，也可以通过改变施加到所选择的存储单元的阵列线的编程脉冲的相对定时来大大减小该效果。在示例性三维反熔丝存储器阵列中，施加到存储单元的阳极区域的正向编程脉冲优选地被定时在更轻掺杂的阴极区域被脉冲为低的时间内。

10. 发明申请

US20060067117A1 Fuse memory cell comprising a diode, the diode serving as the fuse element 审中-公开
标题翻译：保险丝存储单元包括二极管，二极管用作熔丝元件
公开(公告)号：US20060067117A1
公开(公告)日：2006-03-30
申请号：US10955387
申请日：2004-09-29
申请人： Christopher Petti
发明人： Christopher Petti
IPC分类号： G11C17/18 , G11C11/36
CPC分类号： H01L23/5256 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , H01L23/5252 , H01L27/1021 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A memory cell is formed of a semiconductor junction diode interposed between conductors. The cell is programmed by rendering the memory cell very high-resistance, such that current no longer flows between the conductors on application of a read voltage. In this cell the diode behaves as a fuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The silicide may provide a template for crystallization, decreasing the defect density of the silicon and improving its conductivity. It is advantageous to reduce a dielectric layer (such as an oxide, nitride, or oxynitride) intervening between the silicon and the silicon-forming metal during the step of forming the silicide.
摘要翻译：存储单元由介于导体之间的半导体结二极管形成。通过使存储器单元呈现非常高的电阻来编程单元，使得在施加读取电压时电流不再在导体之间流动。在该单元中，二极管表现为保险丝。半导体结二极管包括硅，硅与硅化物接触。硅化物可以提供用于结晶的模板，降低硅的缺陷密度并提高其导电性。有利的是在形成硅化物的步骤期间减少介于硅和形成硅的金属之间的介电层（例如氧化物，氮化物或氮氧化物）。

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