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1. 发明授权

US09135067B2 Resource sharing using process delay 有权
标题翻译：资源共享使用进程延迟
公开(公告)号：US09135067B2
公开(公告)日：2015-09-15
申请号：US13780197
申请日：2013-02-28
申请人： MIPS Technologies, Inc.
发明人： Debasish Chandra
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/5016 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/4812 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.
摘要翻译：提供了减少处理器执行操作所需的共享资源的实例数量和/或执行不影响功能的过程的方法和系统。提供了一种处理器中的处理方法。方面包括确定要由处理器执行的操作将需要使用共享资源。可以发出一个命令，导致第二个操作在N个周期后不使用共享资源。共享资源然后可以用于周期X上的操作的第一方面，然后用于周期X + N处的操作的第二方面。可以根据实施例重新安排第二操作。

2. 发明授权

US09086906B2 Apparatus and method for guest and root register sharing in a virtual machine 有权
标题翻译：在虚拟机中访客和根寄存器共享的装置和方法
公开(公告)号：US09086906B2
公开(公告)日：2015-07-21
申请号：US13436654
申请日：2012-03-30
申请人： Sanjay Patel , Ranjit Joseph Rozario
发明人： Sanjay Patel , Ranjit Joseph Rozario
IPC分类号： G06F9/455
CPC分类号： G06F9/4555
摘要： A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.
摘要翻译：计算机可读存储介质包括可执行指令，以定义具有访客模式控制寄存器的处理器，所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定访客模式控制寄存器包括一个控制位，用于指定访客阻止寄存器状态和共享寄存器状态。根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。访客环境和根本环境支持硬件资源的虚拟化，使得支持多个应用的多个操作系统由硬件资源执行。

3. 发明申请

US20140281413A1 Superforwarding Processor 审中-公开
标题翻译：超前处理器
公开(公告)号：US20140281413A1
公开(公告)日：2014-09-18
申请号：US13828747
申请日：2013-03-14
申请人： MIPS TECHNOLOGIES, INC.
发明人： Qian WANG , Ranganathan Sudhakar
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30032 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： Methods and systems that allow the processor to effectively and efficiently reduce or eliminate the latency associated with instructions that copy the value of one register to another register. A processor includes a superforwarding table, a superforwarding logic block, and a computation engine. The superforwarding table stores an entry, wherein the entry has a valid bit, a key field, and a forward field. The superforwarding logic block determines which register contains the information needed for an instruction. The computation engine executes instructions.
摘要翻译：允许处理器有效地降低或消除与将一个寄存器的值复制到另一个寄存器的指令相关联的延迟的方法和系统。处理器包括超级表，超前逻辑块和计算引擎。超级表格存储条目，其中条目具有有效位，键字段和转发字段。超前逻辑块确定哪个寄存器包含指令所需的信息。计算引擎执行指令。

4. 发明申请

US20140258667A1 Apparatus and Method for Memory Operation Bonding 审中-公开
标题翻译：存储器操作接合的装置和方法
公开(公告)号：US20140258667A1
公开(公告)日：2014-09-11
申请号：US13789394
申请日：2013-03-07
申请人： MIPS TECHNOLOGIES, INC.
发明人： Ranganathan Sudhakar
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G06F9/30043
摘要： A processor is configured to evaluate memory operation bonding criteria to selectively identify memory operation bonding opportunities within a memory access plan. Memory operations are combined in response to the memory operation bonding opportunities to form a revised memory access plan with accelerated memory access.
摘要翻译：处理器被配置为评估存储器操作绑定标准以选择性地识别存储器访问计划中的存储器操作绑定机会。响应于存储器操作结合机会来组合存储器操作以形成具有加速存储器访问的经修改的存储器存取方案。

5. 发明申请

US20140244933A1 Way Lookahead 有权
标题翻译：方式前卫
公开(公告)号：US20140244933A1
公开(公告)日：2014-08-28
申请号：US13781319
申请日：2013-02-28
申请人： MIPS TECHNOLOGIES, INC.
发明人： Ranganathan Sudhakar , Parthiv Pota
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F3/0625 , G06F9/3802 , G06F12/0215 , G06F12/0855 , G06F2212/1028 , G06F2212/452 , Y02D10/13
摘要： Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.
摘要翻译：提供了识别和加强未来指导方法的方法和系统。处理器包括n路组关联高速缓存和指令提取单元。 n路组关联缓存配置为存储指令。指令提取单元与n路组关联高速缓存通信，并且被配置为以第一方式加电，其中第一指示与指令相关联并且指示未来指令所在的方式以及未来指令在哪里当前指令之前的两个或更多个指令。

6. 发明授权

US08327121B2 Data cache receive flop bypass 有权
标题翻译：数据缓存接收触发器旁路
公开(公告)号：US08327121B2
公开(公告)日：2012-12-04
申请号：US12195053
申请日：2008-08-20
申请人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
发明人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
IPC分类号： G06F12/06
CPC分类号： G06F9/3824 , G06F9/3832 , G06F12/0864 , G06F12/0882 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index line in which the requested data is stored. The logic block further provides a disabling signal to the N-way cache for at least one clock cycle if the first and second instructions are detected as pointing to the same cache way.
摘要翻译：如果检测到第一寄存器加载指令之后的第一寄存器加载指令和第二寄存器加载指令，则微处理器包括N路缓存和逻辑块，该逻辑块选择性地启用和禁用N路高速缓存至少一个时钟周期指向存储所请求数据的相同索引行。如果第一和第二指令被检测为指向相同的高速缓存方式，则逻辑块进一步向N路高速缓存提供禁用信号至少一个时钟周期。

7. 发明授权

US08234456B2 Apparatus and method for controlling the exclusivity mode of a level-two cache 有权
标题翻译：用于控制二级缓存的排他性模式的装置和方法
公开(公告)号：US08234456B2
公开(公告)日：2012-07-31
申请号：US13034567
申请日：2011-02-24
申请人： Jinwoo Kim , Darren M. Jones
发明人： Jinwoo Kim , Darren M. Jones
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A method of controlling the exclusivity mode of a level-two cache includes generating level-two cache exclusivity control information at a processor in response to an exclusivity mode indicator, and utilizing the level-two cache exclusivity control information to configure the exclusivity mode of the level-two cache.
摘要翻译：控制二级高速缓存的排他性模式的方法包括响应于独占模式指示器在处理器处产生二级高速缓存独占性控制信息，并且利用二级高速缓存独占性控制信息来配置二级缓存独占性控制信息的排他性模式二级缓存。

8. 发明申请

US20120030392A1 System and Method for Automatic Hardware Interrupt Handling 有权
标题翻译：自动硬件中断处理的系统和方法
公开(公告)号：US20120030392A1
公开(公告)日：2012-02-02
申请号：US12847772
申请日：2010-07-30
申请人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
发明人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , G06F9/30101 , G06F9/30116 , G06F9/327 , G06F9/4812
摘要： A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented
摘要翻译：提供一种处理系统，包括中断引脚，多个寄存器，堆栈指针和自动中断系统。多个寄存器存储多个处理器状态值。当系统检测到中断引脚上的中断时，系统准备进入异常模式，其中自动中断系统导致中断向量被取出，要更新的堆栈指针，以及要从中更新的并行读取的处理器状态值在执行中断服务程序之前，基于更新的堆栈指针，将其存储在存储单元中。还介绍了一种自动硬件中断处理的方法

9. 发明授权

US08078840B2 Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states 有权
标题翻译：基于针对不同线程状态的多个循环输出的优先选择进行线程指令读取
公开(公告)号：US08078840B2
公开(公告)日：2011-12-13
申请号：US12346652
申请日：2008-12-30
申请人： Soumya Banerjee , Michael Gottlieb Jensen
发明人： Soumya Banerjee , Michael Gottlieb Jensen
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3814
摘要： A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.
摘要翻译：公开了并行执行N线程指令的多线程微处理器中的提取指导者。 N线程请求从指令高速缓存获取指令。在给定的选择周期中，某些线程可能没有请求获取指令。提取指导器包括用于以循环方式选择线程之一以将其提取地址提供给指令高速缓存的电路。 1位左电路通过第二加数旋转地增加第一加数，以产生与第一加数的反相并联的和，以产生指示下一个选择的线程的1-hot向量。第一个加数是一个N位向量，如果相应的线程请求从指令高速缓存中获取指令，则每个位都为假。第二个加法是指示最后选择的线程的1-hot向量。在一个实施例中，以最高优先级选择具有空指令缓冲器的线程; 中间优先级的最后发送但未获取的线程; 所有其他线程的优先级最低。线程在最高和最低优先级内选择循环。

10. 发明授权

US08078806B2 Microprocessor with improved data stream prefetching 有权
标题翻译：具有改进的数据流预取的微处理器
公开(公告)号：US08078806B2
公开(公告)日：2011-12-13
申请号：US12911392
申请日：2010-10-25
申请人： Keith E. Diefendorff
发明人： Keith E. Diefendorff
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/1027 , G06F2212/6028
摘要： A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.
摘要翻译：通过总线耦合到系统存储器的微处理器包括指令解码单元，其对指定系统存储器中的数据流的指令和流预取优先级进行解码。微处理器还包括负载/存储单元，其产生负载/存储请求以在系统存储器和微处理器之间传送数据。微处理器还包括流预取单元，其产生多个预取请求以将数据流从系统存储器预取到微处理器中。预取请求指定流预取优先级。微处理器还包括总线接口单元（BIU），其在总线上产生事务请求以响应于加载/存储请求和预取请求在系统存储器和微处理器之间传送数据。基于流预取优先级，BIU针对加载/存储请求的总线事务请求优先处理预取请求的总线事务请求。

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