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1. 发明申请

US20100070257A1 Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files 审中-公开
标题翻译：用于从存储在模拟转储文件中的信息评估电路的方法，系统和计算机程序产品
公开(公告)号：US20100070257A1
公开(公告)日：2010-03-18
申请号：US12210150
申请日：2008-09-12
申请人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
发明人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Disclosed are methods, systems, and computer program products for evaluating performance aspects of electrical circuits, and particularly digital logic circuits. An exemplary method comprises obtaining access to a simulation dump file comprising state indications of the values of a plurality of signals of an electrical circuit at a plurality of simulation time points, and receiving an evaluation task that defines an output based on one or more input signals, with each input signal being a signal for which state indications are provided in the simulation dump file. The method further comprises generating, from the simulation dump file, one or more state representations for the input signals of the evaluation task, with each state representation being representative of the state of an input signal over a period of simulation time, and generating values of the output of the evaluation task at a plurality of simulation time points from the state representations.
摘要翻译：公开了用于评估电路的性能方面的方法，系统和计算机程序产品，特别是数字逻辑电路。一种示例性方法包括获得对包括在多个模拟时间点的电路的多个信号的值的状态指示的模拟转储文件的访问，以及接收基于一个或多个输入信号定义输出的评估任务，每个输入信号是在模拟转储文件中提供状态指示的信号。该方法还包括从模拟转储文件生成用于评估任务的输入信号的一个或多个状态表示，其中每个状态表示在模拟时间周期内代表输入信号的状态，并且产生值在多个模拟时间点从状态表示输出评估任务。

2. 发明申请

US20100049953A1 DATA CACHE RECEIVE FLOP BYPASS 有权
标题翻译： DATA CACHE接收FLOP旁路
公开(公告)号：US20100049953A1
公开(公告)日：2010-02-25
申请号：US12195053
申请日：2008-08-20
申请人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
发明人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
IPC分类号： G06F9/312
CPC分类号： G06F9/3824 , G06F9/3832 , G06F12/0864 , G06F12/0882 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index line in which the requested data is stored. The logic block further provides a disabling signal to the N-way cache for at least one clock cycle if the first and second instructions are detected as pointing to the same cache way.
摘要翻译：如果检测到第一寄存器加载指令之后的第一寄存器加载指令和第二寄存器加载指令，则微处理器包括N路缓存和逻辑块，该逻辑块选择性地启用和禁用N路高速缓存至少一个时钟周期指向存储所请求数据的相同索引行。如果第一和第二指令被检测为指向相同的高速缓存方式，则逻辑块进一步向N路高速缓存提供禁用信号至少一个时钟周期。

3. 发明授权

US08327121B2 Data cache receive flop bypass 有权
标题翻译：数据缓存接收触发器旁路
公开(公告)号：US08327121B2
公开(公告)日：2012-12-04
申请号：US12195053
申请日：2008-08-20
申请人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
发明人： Ajit Karthik Mylavarapu , Sanjai Balakrishnan Athi
IPC分类号： G06F12/06
CPC分类号： G06F9/3824 , G06F9/3832 , G06F12/0864 , G06F12/0882 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index line in which the requested data is stored. The logic block further provides a disabling signal to the N-way cache for at least one clock cycle if the first and second instructions are detected as pointing to the same cache way.
摘要翻译：如果检测到第一寄存器加载指令之后的第一寄存器加载指令和第二寄存器加载指令，则微处理器包括N路缓存和逻辑块，该逻辑块选择性地启用和禁用N路高速缓存至少一个时钟周期指向存储所请求数据的相同索引行。如果第一和第二指令被检测为指向相同的高速缓存方式，则逻辑块进一步向N路高速缓存提供禁用信号至少一个时钟周期。

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