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1. 发明申请

US20120030392A1 System and Method for Automatic Hardware Interrupt Handling 有权
标题翻译：自动硬件中断处理的系统和方法
公开(公告)号：US20120030392A1
公开(公告)日：2012-02-02
申请号：US12847772
申请日：2010-07-30
申请人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
发明人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , G06F9/30101 , G06F9/30116 , G06F9/327 , G06F9/4812
摘要： A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented
摘要翻译：提供一种处理系统，包括中断引脚，多个寄存器，堆栈指针和自动中断系统。多个寄存器存储多个处理器状态值。当系统检测到中断引脚上的中断时，系统准备进入异常模式，其中自动中断系统导致中断向量被取出，要更新的堆栈指针，以及要从中更新的并行读取的处理器状态值在执行中断服务程序之前，基于更新的堆栈指针，将其存储在存储单元中。还介绍了一种自动硬件中断处理的方法

2. 发明申请

US20130191426A1 Merged Floating Point Operation Using a Modebit 有权
标题翻译：使用模式位的合并浮点运算
公开(公告)号：US20130191426A1
公开(公告)日：2013-07-25
申请号：US13358399
申请日：2012-01-25
申请人： David Yiu-Man Lau
发明人： David Yiu-Man Lau
IPC分类号： G06F7/499 , G06F7/483
CPC分类号： G06F9/30014 , G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.
摘要翻译：第一浮点运算单元接收第一和第二变量并执行产生第一输出的第一运算。如果控制位处于第一状态，则第一舍入单元接收并舍入第一输出以产生第二输出。第二浮点运算单元接收第三变量和第一输出或第二输出，并对第三变量和第一输出或第二输出执行第二操作，以产生第三输出。如果控制位处于第一状态，则第二浮点运算单元接收并操作第一输出，如果控制位处于第二状态则接收第二输出。第二舍入单元接收并舍入第三输出。

3. 发明授权

US08392644B2 System and method for automatic hardware interrupt handling 有权
标题翻译：自动硬件中断处理的系统和方法
公开(公告)号：US08392644B2
公开(公告)日：2013-03-05
申请号：US12847772
申请日：2010-07-30
申请人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
发明人： Erik K. Norden , David Yiu-Man Lau , James H. Robinson
IPC分类号： G06F9/48
CPC分类号： G06F13/26 , G06F9/30101 , G06F9/30116 , G06F9/327 , G06F9/4812
摘要： A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.
摘要翻译：提供一种处理系统，包括中断引脚，多个寄存器，堆栈指针和自动中断系统。多个寄存器存储多个处理器状态值。当系统检测到中断引脚上的中断时，系统准备进入异常模式，其中自动中断系统导致中断向量被取出，要更新的堆栈指针，以及要从中更新的并行读取的处理器状态值在执行中断服务程序之前，基于更新的堆栈指针，将其存储在存储单元中。还介绍了一种自动硬件中断处理的方法。

4. 发明申请

US20120323552A1 Apparatus and Method for Hardware Initiation of Emulated Instructions 审中-公开
标题翻译：硬件启动仿真指令的装置和方法
公开(公告)号：US20120323552A1
公开(公告)日：2012-12-20
申请号：US13161354
申请日：2011-06-15
申请人： David Yiu-Man Lau
发明人： David Yiu-Man Lau
IPC分类号： G06F9/455
CPC分类号： G06F11/0721 , G06F9/3865 , G06F9/455 , G06F9/45504 , G06F11/0772 , G06F2009/45591
摘要： A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.
摘要翻译：仿真指令的方法包括识别故障指令。故障指令保存在寄存器中。故障指令与软件仿真操作相关联。通过访问寄存器中的故障指令启动软件仿真操作。

5. 发明申请

US20120324164A1 Programmable Memory Address 审中-公开
标题翻译：可编程存储器地址
公开(公告)号：US20120324164A1
公开(公告)日：2012-12-20
申请号：US13161332
申请日：2011-06-15
申请人： David Yiu-Man Lau
发明人： David Yiu-Man Lau
IPC分类号： G06F12/00 , G06F12/08 , G06F12/14
CPC分类号： G06F12/1036 , G06F12/0888 , G06F12/109 , G06F12/1491 , G06F2212/657
摘要： A method includes storing defined memory address segments and defined memory address segment attributes for a processor. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes.
摘要翻译：一种方法包括存储用于处理器的定义的存储器地址段和定义的存储器地址段属性。处理器根据定义的存储器地址段和定义的存储器地址段属性来操作。

6. 发明授权

US10496461B2 Apparatus and method for hardware initiation of emulated instructions 有权
公开(公告)号：US10496461B2
公开(公告)日：2019-12-03
申请号：US13161354
申请日：2011-06-15
申请人： David Yiu-Man Lau
发明人： David Yiu-Man Lau
IPC分类号： G06F9/455 , G06F11/07 , G06F9/38
CPC分类号： G06F11/0721 , G06F9/455 , G06F9/45504 , G06F11/0772 , G06F9/3865 , G06F2009/45591
摘要： A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

7. 发明授权

US08924454B2 Merged floating point operation using a modebit 有权
标题翻译：使用模式位进行合并浮点运算
公开(公告)号：US08924454B2
公开(公告)日：2014-12-30
申请号：US13358399
申请日：2012-01-25
申请人： David Yiu-Man Lau
发明人： David Yiu-Man Lau
IPC分类号： G06F7/483
CPC分类号： G06F9/30014 , G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.
摘要翻译：第一浮点运算单元接收第一和第二变量并执行产生第一输出的第一运算。如果控制位处于第一状态，则第一舍入单元接收并舍入第一输出以产生第二输出。第二浮点运算单元接收第三变量和第一输出或第二输出，并对第三变量和第一输出或第二输出执行第二操作，以产生第三输出。如果控制位处于第一状态，则第二浮点运算单元接收并操作第一输出，如果控制位处于第二状态则接收第二输出。第二舍入单元接收并舍入第三输出。

8. 发明申请

US20100312991A1 Microprocessor with Compact Instruction Set Architecture 审中-公开
标题翻译：具有紧凑指令集架构的微处理器
公开(公告)号：US20100312991A1
公开(公告)日：2010-12-09
申请号：US12748102
申请日：2010-03-26
申请人： Erik K. NORDEN , James Hippisley Robinson , David Yiu-Man Lau
发明人： Erik K. NORDEN , James Hippisley Robinson , David Yiu-Man Lau
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30178 , G06F9/3001 , G06F9/30043 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30189 , G06F9/322
摘要： A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions, including instructions with encoded arguments determined by statistical analysis and instructions that have the effect of combinations of instructions.
摘要翻译：重新编码的指令集架构（ISA）提供较小的位宽指令或较小和较大位宽指令的组合，以提高指令执行效率并减少代码占用。 ISA可以从具有较大位宽指令的传统ISA重新编码，并且重新编码的ISA可以保持与从其导出的ISA的汇编级兼容性。此外，重新编码的ISA可以具有新的和不同类型的附加指令，包括具有通过统计分析确定的编码参数的指令和具有指令组合的指令的指令。

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