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    • 2. 发明申请
    • Apparatus and method for using a compressed air flow and a vacuum to clean surfaces
    • 使用压缩空气流和真空清洁表面的装置和方法
    • US20070180650A1
    • 2007-08-09
    • US11349764
    • 2006-02-08
    • Thaddeus Gabara
    • Thaddeus Gabara
    • A47L5/14
    • A47L9/08
    • The basic invention uses a positive air pressure port to loosen foreign objects into a cavity and a negative air pressure port to vacuum these objects from the cavity. The positive air pressure port can be used as a substitute for a mechanical beater brush. Removing the beater brush allows the weight of the housing unit to be reduced. The number of positive air pressure ports can be reduced to increase the exit velocity of the air flow out of a single port focusing the energy of the compressed air to a smaller area of the surface which loosens hard to remove foreign objects from the surface. A motor can be used to sweep a single positive air pressure port in a back and fort motion to automatically clean the surface. Finally, the housing unit can be made transparent to view the surface as it is being cleaned.
    • 本发明使用正空气压力端口将异物放入空腔和负空气压力端口,以从空腔中吸收这些物体。 正气压端口可用作机械搅拌刷的替代品。 拆下打浆刷可以减少外壳单元的重量。 可以减少正空气压力端口的数量,以增加空气流出单个端口的出口速度,将压缩空气的能量聚焦到表面的较小区域,其松散以从表面去除异物。 电机可以用于在后面和后面的运动中扫描单个正气压端口,以自动清洁表面。 最后,外壳单元可以做成透明的,以便在清洁表面时观察表面。
    • 3. 发明申请
    • FREQUENCY ADJUSTMENT TECHNIQUES IN COUPLED LC TANK CIRCUITS
    • 耦合液相色谱电路中的频率调整技术
    • US20070170957A1
    • 2007-07-26
    • US11677053
    • 2007-02-21
    • Thaddeus Gabara
    • Thaddeus Gabara
    • H03K5/22
    • G06F1/10H03B5/1212H03B5/1228H03B5/1243H03B27/00H03B2200/0076
    • CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or μprocessor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.
    • CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。 油箱回路提供了一种绝热的行为,可回收无功元件之间的能量,并将传统意义上的损耗降至最低。 磁通联动可以用于编排一些看似独立和分布的CMOS LC电路,以作为一个单元。 提出了可以在包括振荡器阵列的分布式时钟网络环境中使用的几种频率调整技术。 描述了振荡器频率调节的无源磁链,机械和有限状态机技术。
    • 4. 发明申请
    • Fabrication of inductors in transformer based tank circuitry
    • 基于变压器的电路中的电感器的制造
    • US20070018767A1
    • 2007-01-25
    • US11184767
    • 2005-07-19
    • Thaddeus Gabara
    • Thaddeus Gabara
    • H01F5/00
    • H01F17/0006H01F17/0013H01F2017/0053H01L2224/0401H01L2224/05569H01L2224/05572H01L2224/16145H01L2924/19015H01L2924/19042H01L2924/19104
    • Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.
    • 电感或电阻并联使得电感或电阻的组合值根据并联组合规则减小。 本发明通过将多个电感器并联放置来降低电感器的寄生电阻。 此外,通过仔细放置这些电感器,可以使用这些电感器之间的互感将等效电感值增加到接近单个电感器的原始电感值的值。 因此,可以产生具有低得​​多的寄生电阻值的电感。 本发明允许形成高Q电感器,并且对于需要电感的任何电路设计将是有益的。 本发明的另一方面是可以将线圈分隔以最小化涡流损耗。 本发明可以容易地在平面技术中实现。 几个电路的仿真表明,与常规技术相比,功耗可以减少3到4倍。
    • 5. 发明授权
    • Fabrication of inductors in transformer based tank circuitry
    • 基于变压器的电路中的电感器的制造
    • US07786836B2
    • 2010-08-31
    • US11184767
    • 2005-07-19
    • Thaddeus John Gabara
    • Thaddeus John Gabara
    • H01F5/00
    • H01F17/0006H01F17/0013H01F2017/0053H01L2224/0401H01L2224/05569H01L2224/05572H01L2224/16145H01L2924/19015H01L2924/19042H01L2924/19104
    • Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.
    • 电感或电阻并联使得电感或电阻的组合值根据并联组合规则减小。 本发明通过将多个电感器并联放置来降低电感器的寄生电阻。 此外,通过仔细放置这些电感器,可以使用这些电感器之间的互感将等效电感值增加到接近单个电感器的原始电感值的值。 因此,可以产生具有低得​​多的寄生电阻值的电感。 本发明允许形成高Q电感器,并且对于需要电感的任何电路设计将是有益的。 本发明的另一方面是可以将线圈分隔以最小化涡流损耗。 本发明可以容易地在平面技术中实现。 几个电路的仿真表明,与常规技术相比,功耗可以减少3到4倍。
    • 6. 发明授权
    • Reduced eddy current loss in LC tank circuits
    • LC电路中降低的涡流损耗
    • US07429899B2
    • 2008-09-30
    • US11697908
    • 2007-04-09
    • Thaddeus John Gabara
    • Thaddeus John Gabara
    • H03B5/12H01F27/28
    • H03B5/1841H03B5/1212H03B5/1215H03B5/1221H03B5/1228H03B5/124
    • Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.
    • 电感或电阻并联使得电感或电阻的组合值根据并联组合规则减小。 本发明通过将多个电感器并联放置来降低电感器的寄生电阻。 此外,通过仔细放置这些电感器,可以使用这些电感器之间的互感将等效电感值增加到接近单个电感器的原始电感值的值。 因此,可以产生具有低得​​多的寄生电阻值的电感。 本发明允许形成高Q电感器,并且对于需要电感的任何电路设计将是有益的。 本发明的另一方面是可以将线圈分隔以最小化涡流损耗。 本发明可以容易地在平面技术中实现。 几个电路的仿真表明,与常规技术相比,功耗可以减少3到4倍。
    • 8. 发明申请
    • Flux linked LC tank circuits forming distributed clock networks
    • 形成分布式时钟网络的磁通链接LC电路
    • US20070018740A1
    • 2007-01-25
    • US11185001
    • 2005-07-19
    • Thaddeus Gabara
    • Thaddeus Gabara
    • H03B5/08
    • G06F1/10H01L2224/16145H03B5/1212H03B5/1228H03B5/1243H03B2200/0076
    • CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. In one example, the distribution of a 45° separated multi-phase balanced oscillations over the surface of die 1.6 cm×1.6 cm at 10 GHz is expected to dissipate under 10 W and offers a potential to significantly reduce the road map predictions of 100 W. Simulations of several CMOS tank circuits indicate that the power dissipation can be reduced an order of magnitude when compared to conventional techniques. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of an oscillator are described.
    • CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。 油箱回路提供了一种绝热的行为,可回收无功元件之间的能量,并将传统意义上的损耗降至最低。 磁通联动可以用于编排一些看似独立和分布的CMOS LC电路,以作为一个单元。 在一个示例中,在10 GHz处的1.6 cm×1.6 cm的模具表面上的45°分离多相平衡振荡的分布预计将在10 W以下消散,并提供显着降低100 W的路线图预测的潜力 几个CMOS电容电路的仿真表明,与常规技术相比,功耗可以降低一个数量级。 描述了振荡器频率调整的无源磁链,机械和有限状态机技术。
    • 9. 发明申请
    • Frequency adjustment techniques in coupled LC tank circuits
    • 耦合LC电路中的频率调节技术
    • US20070018739A1
    • 2007-01-25
    • US11184428
    • 2005-07-19
    • Thaddeus Gabara
    • Thaddeus Gabara
    • H03B5/08
    • G06F1/10H03B5/1212H03B5/1228H03B5/1243H03B27/00H03B2200/0076
    • CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or μprocessor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.
    • CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。 油箱回路提供了一种绝热的行为,可回收无功元件之间的能量,并将传统意义上的损耗降至最低。 磁通联动可以用于编排一些看似独立和分布的CMOS LC电路,以作为一个单元。 提出了可以在包括振荡器阵列的分布式时钟网络环境中使用的几种频率调整技术。 描述了振荡器频率调节的无源磁链,机械和有限状态机技术。